| 243 | } |
| 244 | |
| 245 | void increment2007(bool rendering, bool by32) { |
| 246 | |
| 247 | if (rendering) |
| 248 | { |
| 249 | //don't do this: |
| 250 | //if (by32) increment_vs(); |
| 251 | //else increment_hsc(); |
| 252 | //do this instead: |
| 253 | increment_vs(); //yes, even if we're moving by 32 |
| 254 | return; |
| 255 | } |
| 256 | |
| 257 | //If the VRAM address increment bit (2000.2) is clear (inc. amt. = 1), all the |
| 258 | //scroll counters are daisy-chained (in the order of HT, VT, H, V, FV) so that |
| 259 | //the carry out of each counter controls the next counter's clock rate. The |
| 260 | //result is that all 5 counters function as a single 15-bit one. Any access to |
| 261 | //2007 clocks the HT counter here. |
| 262 | // |
| 263 | //If the VRAM address increment bit is set (inc. amt. = 32), the only |
| 264 | //difference is that the HT counter is no longer being clocked, and the VT |
| 265 | //counter is now being clocked by access to 2007. |
| 266 | if (by32) { |
| 267 | vt++; |
| 268 | } else { |
| 269 | ht++; |
| 270 | vt += (ht >> 5) & 1; |
| 271 | } |
| 272 | h += (vt >> 5); |
| 273 | v += (h >> 1); |
| 274 | fv += (v >> 1); |
| 275 | ht &= 31; |
| 276 | vt &= 31; |
| 277 | h &= 1; |
| 278 | v &= 1; |
| 279 | fv &= 7; |
| 280 | } |
| 281 | |
| 282 | void debug_log() |
| 283 | { |