| 68 | }; |
| 69 | |
| 70 | static void PSync(void) { |
| 71 | uint8 bankmode = cpu410x[0xb] & 7; |
| 72 | uint8 mask = (bankmode == 0x7) ? (0xff) : (0x3f >> bankmode); |
| 73 | uint32 block = ((cpu410x[0x0] & 0xf0) << 4) + (cpu410x[0xa] & (~mask)); |
| 74 | uint32 pswap = (mmc3cmd & 0x40) << 8; |
| 75 | |
| 76 | // uint8 bank0 = (cpu410x[0xb] & 0x40)?(~1):(cpu410x[0x7]); |
| 77 | // uint8 bank1 = cpu410x[0x8]; |
| 78 | // uint8 bank2 = (cpu410x[0xb] & 0x40)?(cpu410x[0x9]):(~1); |
| 79 | // uint8 bank3 = ~0; |
| 80 | uint8 bank0 = cpu410x[0x7 ^ inv_hack]; |
| 81 | uint8 bank1 = cpu410x[0x8 ^ inv_hack]; |
| 82 | uint8 bank2 = (cpu410x[0xb] & 0x40) ? (cpu410x[0x9]) : (~1); |
| 83 | uint8 bank3 = ~0; |
| 84 | |
| 85 | // FCEU_printf(" PRG: %04x [%02x]",0x8000^pswap,block | (bank0 & mask)); |
| 86 | setprg8(0x8000 ^ pswap, block | (bank0 & mask)); |
| 87 | // FCEU_printf(" %04x [%02x]",0xa000^pswap,block | (bank1 & mask)); |
| 88 | setprg8(0xa000, block | (bank1 & mask)); |
| 89 | // FCEU_printf(" %04x [%02x]",0xc000^pswap,block | (bank2 & mask)); |
| 90 | setprg8(0xc000 ^ pswap, block | (bank2 & mask)); |
| 91 | // FCEU_printf(" %04x [%02x]\n",0xe000^pswap,block | (bank3 & mask)); |
| 92 | setprg8(0xe000, block | (bank3 & mask)); |
| 93 | } |
| 94 | |
| 95 | static void CSync(void) { |
| 96 | static const uint8 midx[8] = { 0, 1, 2, 0, 3, 4, 5, 0 }; |