| 62 | }; |
| 63 | |
| 64 | static void SyncPRG(void) { |
| 65 | switch (mode & 3) { |
| 66 | case 0: |
| 67 | setprg8(0x8000, vrc2_prg[0]); |
| 68 | setprg8(0xA000, vrc2_prg[1]); |
| 69 | setprg8(0xC000, ~1); |
| 70 | setprg8(0xE000, ~0); |
| 71 | break; |
| 72 | case 1: |
| 73 | { |
| 74 | uint32 swap = (mmc3_ctrl >> 5) & 2; |
| 75 | setprg8(0x8000, mmc3_regs[6 + swap]); |
| 76 | setprg8(0xA000, mmc3_regs[7]); |
| 77 | setprg8(0xC000, mmc3_regs[6 + (swap ^ 2)]); |
| 78 | setprg8(0xE000, mmc3_regs[9]); |
| 79 | break; |
| 80 | } |
| 81 | case 2: |
| 82 | case 3: |
| 83 | { |
| 84 | uint8 bank = mmc1_regs[3] & 0xF; |
| 85 | if (mmc1_regs[0] & 8) { |
| 86 | if (mmc1_regs[0] & 4) { |
| 87 | setprg16(0x8000, bank); |
| 88 | setprg16(0xC000, 0x0F); |
| 89 | } else { |
| 90 | setprg16(0x8000, 0); |
| 91 | setprg16(0xC000, bank); |
| 92 | } |
| 93 | } else |
| 94 | setprg32(0x8000, bank >> 1); |
| 95 | break; |
| 96 | } |
| 97 | } |
| 98 | } |
| 99 | |
| 100 | static void SyncCHR(void) { |
| 101 | uint32 base = (mode & 4) << 6; |