| 98 | } |
| 99 | |
| 100 | static void SyncCHR(void) { |
| 101 | uint32 base = (mode & 4) << 6; |
| 102 | switch (mode & 3) { |
| 103 | case 0: |
| 104 | setchr1(0x0000, base | vrc2_chr[0]); |
| 105 | setchr1(0x0400, base | vrc2_chr[1]); |
| 106 | setchr1(0x0800, base | vrc2_chr[2]); |
| 107 | setchr1(0x0c00, base | vrc2_chr[3]); |
| 108 | setchr1(0x1000, base | vrc2_chr[4]); |
| 109 | setchr1(0x1400, base | vrc2_chr[5]); |
| 110 | setchr1(0x1800, base | vrc2_chr[6]); |
| 111 | setchr1(0x1c00, base | vrc2_chr[7]); |
| 112 | break; |
| 113 | case 1: { |
| 114 | uint32 swap = (mmc3_ctrl & 0x80) << 5; |
| 115 | setchr1(0x0000 ^ swap, base | ((mmc3_regs[0]) & 0xFE)); |
| 116 | setchr1(0x0400 ^ swap, base | (mmc3_regs[0] | 1)); |
| 117 | setchr1(0x0800 ^ swap, base | ((mmc3_regs[1]) & 0xFE)); |
| 118 | setchr1(0x0c00 ^ swap, base | (mmc3_regs[1] | 1)); |
| 119 | setchr1(0x1000 ^ swap, base | mmc3_regs[2]); |
| 120 | setchr1(0x1400 ^ swap, base | mmc3_regs[3]); |
| 121 | setchr1(0x1800 ^ swap, base | mmc3_regs[4]); |
| 122 | setchr1(0x1c00 ^ swap, base | mmc3_regs[5]); |
| 123 | break; |
| 124 | } |
| 125 | case 2: |
| 126 | case 3: |
| 127 | if (mmc1_regs[0] & 0x10) { |
| 128 | setchr4(0x0000, mmc1_regs[1]); |
| 129 | setchr4(0x1000, mmc1_regs[2]); |
| 130 | } else |
| 131 | setchr8(mmc1_regs[1] >> 1); |
| 132 | break; |
| 133 | } |
| 134 | } |
| 135 | |
| 136 | static void SyncMIR(void) { |
| 137 | switch (mode & 3) { |