(ep: u32, tx: bool, transfer: &mut UsbEndpointTransferDescriptor)
| 410 | } |
| 411 | |
| 412 | fn schedule_transfer(ep: u32, tx: bool, transfer: &mut UsbEndpointTransferDescriptor) { |
| 413 | let qh = usb_get_queuehead(ep as usize, tx); |
| 414 | let mask = match tx { |
| 415 | true => 1 << (ep + 16), |
| 416 | false => 1 << ep, |
| 417 | }; |
| 418 | |
| 419 | loop { |
| 420 | // Case 2. The queue is not empty. |
| 421 | if qh.last_transfer > 1 { |
| 422 | let last = qh.get_last_transfer(); |
| 423 | |
| 424 | // Add the new dtd to the end of the queue |
| 425 | last.next = (transfer as *const UsbEndpointTransferDescriptor) as u32; |
| 426 | |
| 427 | // If the thing is still primed, hooray we're done. |
| 428 | if (read_word(ENDPTPRIME) & mask) > 0 { |
| 429 | break; |
| 430 | } |
| 431 | |
| 432 | let mut status; |
| 433 | loop { |
| 434 | // Set ATDTW bit to USBCMD |
| 435 | assign(USBCMD, read_word(USBCMD) | (1 << 14)); |
| 436 | // Read status for current queue |
| 437 | status = read_word(ENDPTSTAT) & mask; |
| 438 | // Read atdtw bit |
| 439 | let atdtw = read_word(USBCMD) & (1 << 14); |
| 440 | // If it's zero, restart this process. |
| 441 | // If it's one, we can continue. |
| 442 | if atdtw > 0 { |
| 443 | break; |
| 444 | } else { |
| 445 | assembly!("nop"); |
| 446 | } |
| 447 | } |
| 448 | |
| 449 | // Write atdtw as zero |
| 450 | assign(USBCMD, read_word(USBCMD) & !(1 << 14)); |
| 451 | |
| 452 | // If status bit is set, we're done. Otherwise, fall into Case 1. |
| 453 | if status > 0 { |
| 454 | break; |
| 455 | } |
| 456 | } |
| 457 | |
| 458 | // Case 1. The queue is empty |
| 459 | qh.next = (transfer as *const UsbEndpointTransferDescriptor) as u32; |
| 460 | qh.status = 0; |
| 461 | |
| 462 | usb_prime_endpoint(ep, tx); |
| 463 | qh.set_first_transfer(transfer); |
| 464 | break; |
| 465 | } |
| 466 | |
| 467 | qh.set_last_transfer(transfer); |
| 468 | } |
| 469 |
no test coverage detected