Method codegen_inline_asm

crates/rustc_codegen_nvvm/src/asm.rs:115–303

(
        &mut self,
        template: &[InlineAsmTemplatePiece],
        operands: &[InlineAsmOperandRef<'tcx, Self>],
        options: rustc_ast::InlineAsmOptions,
        line_spans: &[Span],
     

    }

    fn codegen_inline_asm(
        &mut self,
        template: &[InlineAsmTemplatePiece],
        operands: &[InlineAsmOperandRef<'tcx, Self>],
        options: rustc_ast::InlineAsmOptions,
        line_spans: &[Span],
        _inst: Instance,
    ) {
        // Collect the types of output operands
        let mut constraints = vec![];
        let mut output_types = vec![];
        let mut op_idx = FxHashMap::default();
        for (idx, op) in operands.iter().enumerate() {
            match *op {
                InlineAsmOperandRef::Out { reg, late, place } => {
                    let ty = if let Some(ref place) = place {
                        place.layout.llvm_type(self)
                    } else {
                        match reg.reg_class() {
                            InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => {
                                self.type_i16()
                            }
                            InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => {
                                self.type_i32()
                            }
                            InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => {
                                self.type_i64()
                            }
                            _ => unreachable!(),
                        }
                    };
                    output_types.push(ty);
                    op_idx.insert(idx, constraints.len());
                    let prefix = if late { "=" } else { "=&" };
                    constraints.push(format!("{}{}", prefix, reg_to_llvm(reg)));
                }
                InlineAsmOperandRef::InOut {
                    reg,
                    late,
                    in_value,
                    out_place,
                } => {
                    let layout = if let Some(ref out_place) = out_place {
                        &out_place.layout
                    } else {
                        // LLVM required tied operands to have the same type,
                        // so we just use the type of the input.
                        &in_value.layout
                    };
                    let ty = layout.llvm_type(self);
                    output_types.push(ty);
                    op_idx.insert(idx, constraints.len());
                    let prefix = if late { "=" } else { "=&" };
                    constraints.push(format!("{}{}", prefix, reg_to_llvm(reg)));
                }
                _ => {}
            }
        }