| 48 | }; |
| 49 | |
| 50 | Device::Device (const char* cfg) : arena(new TaskArena()) |
| 51 | { |
| 52 | /* check that CPU supports lowest ISA */ |
| 53 | if (!hasISA(ISA)) { |
| 54 | throw_RTCError(RTC_ERROR_UNSUPPORTED_CPU,"CPU does not support " ISA_STR); |
| 55 | } |
| 56 | |
| 57 | /* set default frequency level for detected CPU */ |
| 58 | switch (getCPUModel()) { |
| 59 | case CPU::UNKNOWN: frequency_level = FREQUENCY_SIMD256; break; |
| 60 | case CPU::XEON_ICE_LAKE: frequency_level = FREQUENCY_SIMD256; break; |
| 61 | case CPU::CORE_ICE_LAKE: frequency_level = FREQUENCY_SIMD256; break; |
| 62 | case CPU::CORE_TIGER_LAKE: frequency_level = FREQUENCY_SIMD256; break; |
| 63 | case CPU::CORE_COMET_LAKE: frequency_level = FREQUENCY_SIMD256; break; |
| 64 | case CPU::CORE_CANNON_LAKE:frequency_level = FREQUENCY_SIMD256; break; |
| 65 | case CPU::CORE_KABY_LAKE: frequency_level = FREQUENCY_SIMD256; break; |
| 66 | case CPU::XEON_SKY_LAKE: frequency_level = FREQUENCY_SIMD128; break; |
| 67 | case CPU::CORE_SKY_LAKE: frequency_level = FREQUENCY_SIMD256; break; |
| 68 | case CPU::XEON_BROADWELL: frequency_level = FREQUENCY_SIMD256; break; |
| 69 | case CPU::CORE_BROADWELL: frequency_level = FREQUENCY_SIMD256; break; |
| 70 | case CPU::XEON_HASWELL: frequency_level = FREQUENCY_SIMD256; break; |
| 71 | case CPU::CORE_HASWELL: frequency_level = FREQUENCY_SIMD256; break; |
| 72 | case CPU::XEON_IVY_BRIDGE: frequency_level = FREQUENCY_SIMD256; break; |
| 73 | case CPU::CORE_IVY_BRIDGE: frequency_level = FREQUENCY_SIMD256; break; |
| 74 | case CPU::SANDY_BRIDGE: frequency_level = FREQUENCY_SIMD256; break; |
| 75 | case CPU::NEHALEM: frequency_level = FREQUENCY_SIMD128; break; |
| 76 | case CPU::CORE2: frequency_level = FREQUENCY_SIMD128; break; |
| 77 | case CPU::CORE1: frequency_level = FREQUENCY_SIMD128; break; |
| 78 | case CPU::XEON_PHI_KNIGHTS_MILL : frequency_level = FREQUENCY_SIMD512; break; |
| 79 | case CPU::XEON_PHI_KNIGHTS_LANDING: frequency_level = FREQUENCY_SIMD512; break; |
| 80 | case CPU::ARM: frequency_level = FREQUENCY_SIMD256; break; |
| 81 | } |
| 82 | |
| 83 | /* initialize global state */ |
| 84 | #if defined(EMBREE_CONFIG) |
| 85 | State::parseString(EMBREE_CONFIG); |
| 86 | #endif |
| 87 | State::parseString(cfg); |
| 88 | State::verify(); |
| 89 | |
| 90 | /* check whether selected ISA is supported by the HW, as the user could have forced an unsupported ISA */ |
| 91 | if (!checkISASupport()) { |
| 92 | throw_RTCError(RTC_ERROR_UNSUPPORTED_CPU,"CPU does not support selected ISA"); |
| 93 | } |
| 94 | |
| 95 | /*! do some internal tests */ |
| 96 | assert(isa::Cylinder::verify()); |
| 97 | |
| 98 | /*! enable huge page support if desired */ |
| 99 | #if defined(__WIN32__) |
| 100 | if (State::enable_selockmemoryprivilege) |
| 101 | State::hugepages_success &= win_enable_selockmemoryprivilege(State::verbosity(3)); |
| 102 | #endif |
| 103 | State::hugepages_success &= os_init(State::hugepages,State::verbosity(3)); |
| 104 | |
| 105 | /*! set tessellation cache size */ |
| 106 | setCacheSize( State::tessellation_cache_size ); |
| 107 |
nothing calls this directly
no test coverage detected