| 182 | } |
| 183 | |
| 184 | std::string stringOfCPUModel(CPU model) |
| 185 | { |
| 186 | switch (model) { |
| 187 | case CPU::XEON_ICE_LAKE : return "Xeon Ice Lake"; |
| 188 | case CPU::CORE_ICE_LAKE : return "Core Ice Lake"; |
| 189 | case CPU::CORE_TIGER_LAKE : return "Core Tiger Lake"; |
| 190 | case CPU::CORE_COMET_LAKE : return "Core Comet Lake"; |
| 191 | case CPU::CORE_CANNON_LAKE : return "Core Cannon Lake"; |
| 192 | case CPU::CORE_KABY_LAKE : return "Core Kaby Lake"; |
| 193 | case CPU::XEON_SKY_LAKE : return "Xeon Sky Lake"; |
| 194 | case CPU::CORE_SKY_LAKE : return "Core Sky Lake"; |
| 195 | case CPU::XEON_PHI_KNIGHTS_MILL : return "Xeon Phi Knights Mill"; |
| 196 | case CPU::XEON_PHI_KNIGHTS_LANDING: return "Xeon Phi Knights Landing"; |
| 197 | case CPU::XEON_BROADWELL : return "Xeon Broadwell"; |
| 198 | case CPU::CORE_BROADWELL : return "Core Broadwell"; |
| 199 | case CPU::XEON_HASWELL : return "Xeon Haswell"; |
| 200 | case CPU::CORE_HASWELL : return "Core Haswell"; |
| 201 | case CPU::XEON_IVY_BRIDGE : return "Xeon Ivy Bridge"; |
| 202 | case CPU::CORE_IVY_BRIDGE : return "Core Ivy Bridge"; |
| 203 | case CPU::SANDY_BRIDGE : return "Sandy Bridge"; |
| 204 | case CPU::NEHALEM : return "Nehalem"; |
| 205 | case CPU::CORE2 : return "Core2"; |
| 206 | case CPU::CORE1 : return "Core"; |
| 207 | case CPU::ARM : return "ARM"; |
| 208 | case CPU::UNKNOWN : return "Unknown CPU"; |
| 209 | } |
| 210 | return "Unknown CPU (error)"; |
| 211 | } |
| 212 | |
| 213 | #if defined(__X86_ASM__) |
| 214 | /* constants to access destination registers of CPUID instruction */ |