Function arm_gic_dist_init

libcpu/aarch64/common/gic.c:373–447

}

int arm_gic_dist_init(rt_uint64_t index, rt_uint64_t dist_base, int irq_start)
{
    unsigned int gic_type, i;
    rt_uint64_t cpumask = 1U << 0U;

    RT_ASSERT(index < ARM_GIC_MAX_NR);

    _gic_table[index].dist_hw_base = dist_base;
    _gic_table[index].offset = irq_start;

    /* Find out how many interrupts are supported. */
    gic_type = GIC_DIST_TYPE(dist_base);
    _gic_max_irq = ((gic_type & 0x1fU) + 1U) * 32U;

    /*
     * The GIC only supports up to 1020 interrupt sources.
     * Limit this to either the architected maximum, or the
     * platform maximum.
     */
    if (_gic_max_irq > 1020U)
    {
        _gic_max_irq = 1020U;
    }
    if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */
    {
        _gic_max_irq = ARM_GIC_NR_IRQS;
    }

    cpumask |= cpumask << 8U;
    cpumask |= cpumask << 16U;
    cpumask |= cpumask << 24U;

    GIC_DIST_CTRL(dist_base) = 0x0U;

    /* Set all global interrupts to be level triggered, active low. */
    for (i = 32U; i < _gic_max_irq; i += 16U)
    {
        GIC_DIST_CONFIG(dist_base, i) = 0x0U;
    }

    /* Set all global interrupts to this CPU only. */
    for (i = 32U; i < _gic_max_irq; i += 4U)
    {
        GIC_DIST_TARGET(dist_base, i) = cpumask;
    }

    /* Set priority on all interrupts. */
    for (i = 0U; i < _gic_max_irq; i += 4U)
    {
        GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0U;
    }

    /* Disable all interrupts. */
    for (i = 0U; i < _gic_max_irq; i += 32U)
    {
        GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffffU;
    }