| 447 | } |
| 448 | |
| 449 | int arm_gic_cpu_init(rt_uint64_t index, rt_uint64_t cpu_base) |
| 450 | { |
| 451 | RT_ASSERT(index < ARM_GIC_MAX_NR); |
| 452 | |
| 453 | if (!_gic_table[index].cpu_hw_base) |
| 454 | { |
| 455 | _gic_table[index].cpu_hw_base = cpu_base; |
| 456 | } |
| 457 | cpu_base = _gic_table[index].cpu_hw_base; |
| 458 | |
| 459 | GIC_CPU_PRIMASK(cpu_base) = 0xf0U; |
| 460 | GIC_CPU_BINPOINT(cpu_base) = 0x7U; |
| 461 | /* Enable CPU interrupt */ |
| 462 | GIC_CPU_CTRL(cpu_base) = 0x01U; |
| 463 | |
| 464 | return 0; |
| 465 | } |
| 466 | |
| 467 | void arm_gic_dump_type(rt_uint64_t index) |
| 468 | { |
no outgoing calls
no test coverage detected