Function spi_bit_xfer

components/drivers/spi/dev_spi_bit_ops.c:468–560

}

rt_ssize_t spi_bit_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
{
    struct rt_spi_bit_obj *obj = rt_container_of(device->bus, struct rt_spi_bit_obj, bus);
    struct rt_spi_bit_ops *ops = obj->ops;
    struct rt_spi_configuration *config = &obj->config;
    rt_base_t cs_pin = device->cs_pin;
    rt_ssize_t length = 0;

    RT_ASSERT(device != NULL);
    RT_ASSERT(message != NULL);

#ifdef RT_SPI_BITOPS_DEBUG
    if (!ops->tog_sclk || !ops->set_sclk || !ops->get_sclk)
    {
        LOG_E("SPI bus error, SCLK line not defined");
    }
    if (!ops->set_mosi || !ops->get_mosi)
    {
        LOG_E("SPI bus error, MOSI line not defined");
    }
    if (!ops->set_miso || !ops->get_miso)
    {
        LOG_E("SPI bus error, MISO line not defined");
    }
#endif

    /* take CS */
    if (message->cs_take && !(device->config.mode & RT_SPI_NO_CS) && (cs_pin != PIN_NONE))
    {
        LOG_I("spi take cs\n");
        if (device->config.mode & RT_SPI_CS_HIGH)
        {
            rt_pin_write(cs_pin, PIN_HIGH);
        }
        else
        {
            rt_pin_write(cs_pin, PIN_LOW);
        }
        spi_delay(ops);
    }

        /* spi phase */
        if ((config->mode & RT_SPI_CPHA))
        {
            spi_delay(ops);
            TOG_SCLK(ops);
        }
    if (config->mode & RT_SPI_3WIRE)
    {
        if (config->data_width <= 8)
        {
            length = spi_xfer_3line_data8(ops, config, message->send_buf, message->recv_buf, message->length);
        }
        else if (config->data_width <= 16)
        {
            length = spi_xfer_3line_data16(ops, config, message->send_buf, message->recv_buf, message->length);
        }
    }