* Serial interrupt routines */
| 294 | * Serial interrupt routines |
| 295 | */ |
| 296 | rt_inline int _serial_int_rx(struct rt_serial_device *serial, rt_uint8_t *data, int length) |
| 297 | { |
| 298 | int size; |
| 299 | struct rt_serial_rx_fifo* rx_fifo; |
| 300 | |
| 301 | RT_ASSERT(serial != RT_NULL); |
| 302 | size = length; |
| 303 | |
| 304 | rx_fifo = (struct rt_serial_rx_fifo*) serial->serial_rx; |
| 305 | RT_ASSERT(rx_fifo != RT_NULL); |
| 306 | |
| 307 | #ifdef RT_USING_SERIAL_BYPASS |
| 308 | if (serial->bypass) |
| 309 | { |
| 310 | rt_bypass_work_straight(serial); |
| 311 | while (length) |
| 312 | { |
| 313 | rt_uint8_t ch; |
| 314 | if (!rt_bypass_getchar(serial, &ch)) |
| 315 | break; |
| 316 | |
| 317 | *data = ch & 0xff; |
| 318 | data++; length--; |
| 319 | } |
| 320 | |
| 321 | return size - length; |
| 322 | } |
| 323 | #endif |
| 324 | /* read from software FIFO */ |
| 325 | while (length) |
| 326 | { |
| 327 | int ch; |
| 328 | rt_base_t level; |
| 329 | |
| 330 | /* disable interrupt */ |
| 331 | level = rt_spin_lock_irqsave(&(serial->spinlock)); |
| 332 | |
| 333 | /* there's no data: */ |
| 334 | if ((rx_fifo->get_index == rx_fifo->put_index) && (rx_fifo->is_full == RT_FALSE)) |
| 335 | { |
| 336 | /* no data, enable interrupt and break out */ |
| 337 | rt_spin_unlock_irqrestore(&(serial->spinlock), level); |
| 338 | break; |
| 339 | } |
| 340 | |
| 341 | /* otherwise there's the data: */ |
| 342 | ch = rx_fifo->buffer[rx_fifo->get_index]; |
| 343 | rx_fifo->get_index += 1; |
| 344 | if (rx_fifo->get_index >= serial->config.bufsz) rx_fifo->get_index = 0; |
| 345 | |
| 346 | if (rx_fifo->is_full == RT_TRUE) |
| 347 | { |
| 348 | rx_fifo->is_full = RT_FALSE; |
| 349 | } |
| 350 | |
| 351 | /* enable interrupt */ |
| 352 | rt_spin_unlock_irqrestore(&(serial->spinlock), level); |
| 353 |
no test coverage detected