| 361 | } |
| 362 | |
| 363 | static rt_err_t lpi_flush_config(struct gicv3_its *its, rt_uint8_t *conf, |
| 364 | struct rt_pic_irq *pirq) |
| 365 | { |
| 366 | struct its_command cmd; |
| 367 | struct its_map *map = pirq->msi_desc->priv; |
| 368 | |
| 369 | if (its->gic->redist_flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING) |
| 370 | { |
| 371 | /* Clean D-cache under command */ |
| 372 | rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, conf, sizeof(*conf)); |
| 373 | } |
| 374 | else |
| 375 | { |
| 376 | /* DSB inner shareable, store */ |
| 377 | rt_hw_wmb(); |
| 378 | } |
| 379 | |
| 380 | rt_memset(&cmd, 0, sizeof(cmd)); |
| 381 | its_encode_cmd(&cmd, GITS_CMD_INV); |
| 382 | its_encode_device_id(&cmd, its_pirq_device_id(its, pirq)); |
| 383 | its_encode_event_id(&cmd, its_pirq_event_id(its, pirq)); |
| 384 | |
| 385 | return its_cmd_submit(its, &cmd, map, RT_FALSE); |
| 386 | } |
| 387 | |
| 388 | rt_inline void *gicr_rd_base_percpu(struct gicv3 *gic) |
| 389 | { |
no test coverage detected