| 206 | } |
| 207 | |
| 208 | static rt_err_t gicv2_irq_set_affinity(struct rt_pic_irq *pirq, rt_bitmap_t *affinity) |
| 209 | { |
| 210 | int hwirq = pirq->hwirq; |
| 211 | struct gicv2 *gic = raw_to_gicv2(pirq->pic); |
| 212 | rt_uint32_t target_list = ((rt_uint8_t *)affinity)[gic - &_gicv2_list[0]]; |
| 213 | rt_uint8_t valb = _gicv2_cpumask_map[__rt_ffs(target_list) - 1]; |
| 214 | void *io_addr = gic->dist_base + GIC_DIST_TARGET + hwirq; |
| 215 | |
| 216 | if (valb == 0xfe) |
| 217 | { |
| 218 | return -RT_EIO; |
| 219 | } |
| 220 | |
| 221 | if (needs_rmw_access) |
| 222 | { |
| 223 | /* RMW write byte */ |
| 224 | rt_uint32_t val; |
| 225 | rt_ubase_t level; |
| 226 | rt_ubase_t offset = (rt_ubase_t)io_addr & 3UL, shift = offset * 8; |
| 227 | static RT_DEFINE_SPINLOCK(rmw_lock); |
| 228 | |
| 229 | level = rt_spin_lock_irqsave(&rmw_lock); |
| 230 | |
| 231 | io_addr -= offset; |
| 232 | val = HWREG32(io_addr); |
| 233 | val &= ~RT_GENMASK(shift + 7, shift); |
| 234 | val |= valb << shift; |
| 235 | HWREG32(io_addr) = val; |
| 236 | |
| 237 | rt_spin_unlock_irqrestore(&rmw_lock, level); |
| 238 | } |
| 239 | else |
| 240 | { |
| 241 | HWREG8(io_addr) = valb; |
| 242 | } |
| 243 | |
| 244 | return RT_EOK; |
| 245 | } |
| 246 | |
| 247 | static rt_err_t gicv2_irq_set_triger_mode(struct rt_pic_irq *pirq, rt_uint32_t mode) |
| 248 | { |
nothing calls this directly
no test coverage detected