| 202 | } |
| 203 | |
| 204 | static void pci_configure_ari(struct rt_pci_device *pdev) |
| 205 | { |
| 206 | rt_uint32_t cap, ctl2_ari; |
| 207 | struct rt_pci_device *bridge; |
| 208 | |
| 209 | if (!rt_pci_is_pcie(pdev) || pdev->devfn) |
| 210 | { |
| 211 | return; |
| 212 | } |
| 213 | |
| 214 | bridge = pdev->bus->self; |
| 215 | |
| 216 | if (rt_pci_is_root_bus(pdev->bus) || !bridge) |
| 217 | { |
| 218 | return; |
| 219 | } |
| 220 | |
| 221 | rt_pci_read_config_u32(bridge, bridge->pcie_cap + PCIER_DEVICE_CAP2, &cap); |
| 222 | if (!(cap & PCIEM_CAP2_ARI)) |
| 223 | { |
| 224 | return; |
| 225 | } |
| 226 | |
| 227 | rt_pci_read_config_u32(bridge, bridge->pcie_cap + PCIER_DEVICE_CTL2, &ctl2_ari); |
| 228 | |
| 229 | if (rt_pci_find_ext_capability(pdev, PCIZ_ARI)) |
| 230 | { |
| 231 | ctl2_ari |= PCIEM_CTL2_ARI; |
| 232 | bridge->ari_enabled = RT_TRUE; |
| 233 | } |
| 234 | else |
| 235 | { |
| 236 | ctl2_ari &= ~PCIEM_CTL2_ARI; |
| 237 | bridge->ari_enabled = RT_FALSE; |
| 238 | } |
| 239 | |
| 240 | rt_pci_write_config_u32(bridge, bridge->pcie_cap + PCIER_DEVICE_CTL2, ctl2_ari); |
| 241 | } |
| 242 | |
| 243 | static rt_uint16_t pci_cfg_space_size_ext(struct rt_pci_device *pdev) |
| 244 | { |
no test coverage detected