Function msi_capability_init

components/drivers/pci/msi/msi.c:593–651

}

static rt_ssize_t msi_capability_init(struct rt_pci_device *pdev,
        int nvec, RT_IRQ_AFFINITY_DECLARE((*affinities)))
{
    rt_err_t err;
    struct rt_pci_msi_desc *desc;

    msi_write_enable(pdev, RT_FALSE);

    spin_lock(&pdev->msi_lock);

    if (!(err = msi_setup_msi_desc(pdev, nvec)))
    {
        /* All MSIs are unmasked by default; mask them all */
        desc = rt_pci_msi_first_desc(pdev);
        msi_mask(&desc->msi, msi_multi_mask(&desc->msi), pdev);

        if (!(err = rt_pci_msi_setup_irqs(pdev, nvec, PCIY_MSI)))
        {
            err = msi_verify_entries(pdev);
        }

        if (err)
        {
            msi_unmask(&desc->msi, msi_multi_mask(&desc->msi), pdev);
        }
    }

    spin_unlock(&pdev->msi_lock);

    if (err)
    {
        rt_pci_msi_free_irqs(pdev);

        LOG_E("%s: Setup %s interrupts(%d) error = %s",
                rt_dm_dev_get_name(&pdev->parent), "MSI", nvec, rt_strerror(err));

        return err;
    }

    if (affinities)
    {
        for (int idx = 0; idx < nvec; ++idx)
        {
            msi_affinity_init(desc, idx, affinities[idx]);
        }
    }

    /* Disable INTX */
    rt_pci_intx(pdev, RT_FALSE);

    /* Set MSI enabled bits */
    msi_write_enable(pdev, RT_TRUE);

    pdev->irq = desc->irq;

    pdev->msi_enabled = RT_TRUE;

    return nvec;