| 36 | } |
| 37 | |
| 38 | static rt_err_t ofw_parse_irq_map(struct rt_ofw_node *np, struct rt_ofw_cell_args *irq_args) |
| 39 | { |
| 40 | rt_err_t err = RT_EOK; |
| 41 | rt_phandle ic_phandle = 0; |
| 42 | rt_ssize_t map_len, map_mask_len; |
| 43 | struct rt_ofw_node *ic_np = RT_NULL; |
| 44 | const fdt32_t *addr, *map, *map_mask; |
| 45 | int child_address_cells, child_interrupt_cells; |
| 46 | int parent_address_cells = 0, parent_interrupt_cells = 0; |
| 47 | int addr_cells, pin_cells, icaddr_cells, idx1, idx2, limit; |
| 48 | |
| 49 | /* |
| 50 | * interrupt-map: |
| 51 | * An interrupt-map is a property on a nexus node that bridges one |
| 52 | * interrupt domain with a set of parent interrupt domains and specifies |
| 53 | * how interrupt specifiers in the child domain are mapped to |
| 54 | * their respective parent domains. |
| 55 | * |
| 56 | * The interrupt map is a table where each row is a mapping entry |
| 57 | * consisting of five components: child unit address, child interrupt |
| 58 | * specifier, interrupt-parent, parent unit address, parent interrupt |
| 59 | * specifier. |
| 60 | * |
| 61 | * child unit address |
| 62 | * The unit address of the child node being mapped. The number of |
| 63 | * 32-bit cells required to specify this is described by the |
| 64 | * #address-cells property of the bus node on which the child is |
| 65 | * located. |
| 66 | * |
| 67 | * child interrupt specifier |
| 68 | * The interrupt specifier of the child node being mapped. The number |
| 69 | * of 32-bit cells required to specify this component is described by |
| 70 | * the #interrupt-cells property of this node-the nexus node containing |
| 71 | * the interrupt-map property. |
| 72 | * |
| 73 | * interrupt-parent |
| 74 | * A single <phandle> value that points to the interrupt parent to |
| 75 | * which the child domain is being mapped. |
| 76 | * |
| 77 | * parent unit address |
| 78 | * The unit address in the domain of the interrupt parent. The number |
| 79 | * of 32-bit cells required to specify this address is described by the |
| 80 | * #address-cells property of the node pointed to by the |
| 81 | * interrupt-parent field. |
| 82 | * |
| 83 | * parent interrupt specifier |
| 84 | * The interrupt specifier in the parent domain. The number of 32-bit |
| 85 | * cells required to specify this component is described by the |
| 86 | * #interrupt-cells property of the node pointed to by the |
| 87 | * interrupt-parent field. |
| 88 | * |
| 89 | * Lookups are performed on the interrupt mapping table by matching a |
| 90 | * unit-address/interrupt specifier pair against the child components in |
| 91 | * the interrupt-map. Because some fields in the unit interrupt specifier |
| 92 | * may not be relevant, a mask is applied before the lookup is done. |
| 93 | * Example: |
| 94 | * |
| 95 | * pic: interrupt-controller@0 { |
no test coverage detected