| 880 | } |
| 881 | |
| 882 | static rt_err_t nvme_configure_admin_queue(struct rt_nvme_controller *nvme) |
| 883 | { |
| 884 | rt_err_t err; |
| 885 | int irq; |
| 886 | char name[RT_NAME_MAX]; |
| 887 | rt_uint32_t aqa; |
| 888 | rt_uint32_t page_shift = ARCH_PAGE_SHIFT; |
| 889 | rt_uint32_t page_min = RT_NVME_CAP_MPSMIN(nvme->cap) + 12; |
| 890 | rt_uint32_t page_max = RT_NVME_CAP_MPSMAX(nvme->cap) + 12; |
| 891 | struct rt_nvme_queue *admin_queue; |
| 892 | |
| 893 | if (page_shift < page_min) |
| 894 | { |
| 895 | LOG_E("Device %s page size (%u) %s than host (%u)", |
| 896 | "minimum", 1 << page_min, "larger", 1 << page_shift); |
| 897 | return -RT_EINVAL; |
| 898 | } |
| 899 | |
| 900 | if (page_shift > page_max) |
| 901 | { |
| 902 | LOG_W("Device %s page size (%u) %s than host (%u)", |
| 903 | "maximum", 1 << page_max, "smaller", 1 << page_shift); |
| 904 | page_shift = page_max; |
| 905 | } |
| 906 | |
| 907 | if ((err = nvme_disable_ctrl(nvme))) |
| 908 | { |
| 909 | return err; |
| 910 | } |
| 911 | |
| 912 | admin_queue = nvme_alloc_queue(nvme, 0, RT_NVME_AQ_DEPTH); |
| 913 | |
| 914 | if (rt_is_err(admin_queue)) |
| 915 | { |
| 916 | return rt_ptr_err(admin_queue); |
| 917 | } |
| 918 | |
| 919 | aqa = admin_queue->depth - 1; |
| 920 | aqa |= aqa << 16; |
| 921 | |
| 922 | nvme->page_shift = page_shift; |
| 923 | nvme->page_size = 1U << page_shift; |
| 924 | |
| 925 | nvme->ctrl_config = RT_NVME_CC_CSS_NVM; |
| 926 | nvme->ctrl_config |= (page_shift - 12) << RT_NVME_CC_MPS_SHIFT; |
| 927 | nvme->ctrl_config |= RT_NVME_CC_ARB_RR | RT_NVME_CC_SHN_NONE; |
| 928 | nvme->ctrl_config |= RT_NVME_CC_IOSQES | RT_NVME_CC_IOCQES; |
| 929 | |
| 930 | nvme_writel(nvme, RT_NVME_REG_AQA, aqa); |
| 931 | nvme_writeq(nvme, RT_NVME_REG_ASQ, admin_queue->sq_cmds_phy); |
| 932 | nvme_writeq(nvme, RT_NVME_REG_ACQ, admin_queue->cq_entry_phy); |
| 933 | |
| 934 | if ((err = nvme_enable_ctrl(nvme))) |
| 935 | { |
| 936 | nvme_free_queue(admin_queue); |
| 937 | |
| 938 | return err; |
| 939 | } |
no test coverage detected