| 726 | } |
| 727 | |
| 728 | static rt_err_t nvme_attach_queue(struct rt_nvme_queue *queue, rt_uint8_t opcode) |
| 729 | { |
| 730 | struct rt_nvme_command cmd; |
| 731 | struct rt_nvme_controller *nvme = queue->nvme; |
| 732 | rt_uint16_t flags = RT_NVME_QUEUE_PHYS_CONTIG; |
| 733 | |
| 734 | rt_memset(&cmd, 0, sizeof(cmd)); |
| 735 | |
| 736 | if (opcode == RT_NVME_ADMIN_OPCODE_CREATE_CQ) |
| 737 | { |
| 738 | cmd.create_cq.opcode = opcode; |
| 739 | cmd.create_cq.prp1 = rt_cpu_to_le64(queue->cq_entry_phy); |
| 740 | cmd.create_cq.cqid = rt_cpu_to_le16(queue->qid); |
| 741 | cmd.create_cq.qsize = rt_cpu_to_le16(queue->depth - 1); |
| 742 | cmd.create_cq.cq_flags = rt_cpu_to_le16(flags | RT_NVME_CQ_IRQ_ENABLED); |
| 743 | cmd.create_cq.irq_vector = rt_cpu_to_le16(nvme->irqs_nr > 1 ? queue->qid : 0); |
| 744 | } |
| 745 | else if (opcode == RT_NVME_ADMIN_OPCODE_CREATE_SQ) |
| 746 | { |
| 747 | cmd.create_sq.opcode = opcode; |
| 748 | cmd.create_sq.prp1 = rt_cpu_to_le64(queue->sq_cmds_phy); |
| 749 | cmd.create_sq.sqid = rt_cpu_to_le16(queue->qid); |
| 750 | cmd.create_sq.qsize = rt_cpu_to_le16(queue->depth - 1); |
| 751 | cmd.create_sq.sq_flags = rt_cpu_to_le16(flags | RT_NVME_SQ_PRIO_MEDIUM); |
| 752 | cmd.create_sq.cqid = rt_cpu_to_le16(queue->qid); |
| 753 | } |
| 754 | else |
| 755 | { |
| 756 | LOG_E("What the fuck opcode = %x", opcode); |
| 757 | RT_ASSERT(0); |
| 758 | } |
| 759 | |
| 760 | return nvme_submit_cmd(&nvme->admin_queue, &cmd); |
| 761 | } |
| 762 | |
| 763 | rt_inline rt_err_t nvme_attach_queue_sq(struct rt_nvme_queue *queue) |
| 764 | { |
no test coverage detected