Function dfs_aspace_mmap

components/dfs/dfs_v2/src/dfs_pcache.c:1818–1873

* @brief Map a file page into virtual address space * * This function maps a file page into the specified virtual address space, handling * memory allocation, page lookup, and cache synchronization. It ensures proper * memory visibility across different CPU architectures with cache operations. * * @param[in] file Pointer to the file structure * @param[in] varea Pointer to the virtual a

 *       manages the mapping structure lifecycle through proper allocation/free.
 */
void *dfs_aspace_mmap(struct dfs_file *file, struct rt_varea *varea, void *vaddr)
{
    void *ret = RT_NULL;
    struct dfs_page *page;
    struct dfs_aspace *aspace = file->vnode->aspace;
    rt_aspace_t target_aspace = varea->aspace;

    page = dfs_page_lookup(file, dfs_aspace_fpos(varea, vaddr));
    if (page)
    {
        struct dfs_mmap *map = (struct dfs_mmap *)rt_calloc(1, sizeof(struct dfs_mmap));
        if (map)
        {
            void *pg_vaddr = page->page;
            void *pg_paddr = rt_kmem_v2p(pg_vaddr);
            int err = rt_varea_map_range(varea, vaddr, pg_paddr, page->size);
            if (err == RT_EOK)
            {
                /**
                 * Note: While the page is mapped into user area, the data writing into the page
                 * is not guaranteed to be visible for machines with the *weak* memory model and
                 * those Harvard architecture (especially for those ARM64) cores for their
                 * out-of-order pipelines of data buffer. Besides if the instruction cache in the
                 * L1 memory system is a VIPT cache, there are chances to have the alias matching
                 * entry if we reuse the same page frame and map it into the same virtual address
                 * of the previous one.
                 *
                 * That's why we have to do synchronization and cleanup manually to ensure that
                 * fetching of the next instruction can see the coherent data with the data cache,
                 * TLB, MMU, main memory, and all the other observers in the computer system.
                 */
                rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, vaddr, ARCH_PAGE_SIZE);
                rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE, vaddr, ARCH_PAGE_SIZE);

                ret = pg_vaddr;
                map->aspace = target_aspace;
                map->vaddr = vaddr;
                dfs_aspace_lock(aspace);
                rt_list_insert_after(&page->mmap_head, &map->mmap_node);
                dfs_page_release(page);
                dfs_aspace_unlock(aspace);
            }
            else
            {
                dfs_page_release(page);
                rt_free(map);
            }
        }
        else
        {
            dfs_page_release(page);
        }
    }

    return ret;
}

/**