Gets the current Ethernet MAC interrupt status. \param ui32Base is the base address of the Ethernet MAC. \param bMasked is \b true to return the masked interrupt status or \b false to return the unmasked status. This function returns the interrupt status for the Ethernet MAC. Either the raw interrupt status or the status of interrupts that are allowed to reflect to the processor can be returned
| 2682 | // |
| 2683 | //***************************************************************************** |
| 2684 | uint32_t |
| 2685 | EMACIntStatus(uint32_t ui32Base, bool bMasked) |
| 2686 | { |
| 2687 | uint32_t ui32Val, ui32PHYStat; |
| 2688 | |
| 2689 | // |
| 2690 | // Parameter sanity check. |
| 2691 | // |
| 2692 | ASSERT(ui32Base == EMAC0_BASE); |
| 2693 | |
| 2694 | // |
| 2695 | // Get the unmasked interrupt status and clear any unwanted status fields. |
| 2696 | // |
| 2697 | ui32Val = HWREG(ui32Base + EMAC_O_DMARIS); |
| 2698 | ui32Val &= ~(EMAC_DMARIS_AE_M | EMAC_DMARIS_TS_M | EMAC_DMARIS_RS_M); |
| 2699 | |
| 2700 | // |
| 2701 | // This peripheral doesn't have a masked interrupt status register |
| 2702 | // so perform the masking manually. Note that only the bottom 16 bits |
| 2703 | // of the register can be masked so make sure we take this into account. |
| 2704 | // |
| 2705 | if(bMasked) |
| 2706 | { |
| 2707 | ui32Val &= (EMAC_NON_MASKED_INTS | HWREG(ui32Base + EMAC_O_DMAIM)); |
| 2708 | } |
| 2709 | |
| 2710 | // |
| 2711 | // Read the PHY interrupt status. |
| 2712 | // |
| 2713 | if(bMasked) |
| 2714 | { |
| 2715 | ui32PHYStat = HWREG(ui32Base + EMAC_O_EPHYMISC); |
| 2716 | } |
| 2717 | else |
| 2718 | { |
| 2719 | ui32PHYStat = HWREG(ui32Base + EMAC_O_EPHYRIS); |
| 2720 | } |
| 2721 | |
| 2722 | // |
| 2723 | // If the PHY interrupt is reported, add the appropriate flag to the |
| 2724 | // return value. |
| 2725 | // |
| 2726 | if(ui32PHYStat & EMAC_EPHYMISC_INT) |
| 2727 | { |
| 2728 | ui32Val |= EMAC_INT_PHY; |
| 2729 | } |
| 2730 | |
| 2731 | return(ui32Val); |
| 2732 | } |
| 2733 | |
| 2734 | //***************************************************************************** |
| 2735 | // |