* ��ʼ����ʱ��������ʼ��ʱ * @timer_info ��ʱ���Ͷ�ʱʱ����Ϣ */
| 60 | * @timer_info ��ʱ���Ͷ�ʱʱ����Ϣ |
| 61 | */ |
| 62 | void timer_init(timer_info_t *timer_info) |
| 63 | { |
| 64 | unsigned int timer_reg_base = 0; // �Ĵ�������ַ |
| 65 | unsigned long timer_clk = 0; // Ӳ����ʱ����ʱ�� |
| 66 | unsigned long tmp; |
| 67 | unsigned int ctrl = 0; // ���ƼĴ����еĿ�����Ϣ |
| 68 | |
| 69 | // ���� |
| 70 | if (NULL == timer_info) |
| 71 | { |
| 72 | return ; |
| 73 | } |
| 74 | |
| 75 | /* |
| 76 | * �Ѷ�ʱʱ�任��Ϊ��������ֵ |
| 77 | * ������ֵ = ��ʱ����ʱ�� * ��ʱʱ��(��λns) / 1000000000 |
| 78 | * ��о1c�Ķ�ʱ��ʱ��ΪAPBʱ�ӣ��ﵽ126Mhz�� |
| 79 | * Ϊ���������̷����������������ֶ��Ż�����ļ���ʽ��Ҳ���Բ��ø������� |
| 80 | */ |
| 81 | timer_clk = clk_get_apb_rate(); |
| 82 | tmp = (timer_clk / 1000000) * (timer_info->time_ns / 1000); // ��1000000000���Ϊ1000000��1000 |
| 83 | tmp = MIN(tmp, TIMER_COUNTER_MAX); |
| 84 | |
| 85 | // ���ƼĴ�����Ϣ |
| 86 | ctrl = (1 << LS1C_PWM_INT_LRC_EN) |
| 87 | | (0 << LS1C_PWM_INT_HRC_EN) |
| 88 | | (0 << LS1C_PWM_CNTR_RST) |
| 89 | | (0 << LS1C_PWM_INT_SR) |
| 90 | | (1 << LS1C_PWM_INTEN) |
| 91 | | (1 << LS1C_PWM_SINGLE) |
| 92 | | (1 << LS1C_PWM_OE) |
| 93 | | (1 << LS1C_PWM_CNT_EN); |
| 94 | |
| 95 | // ���ø����Ĵ��� |
| 96 | timer_reg_base = timer_get_reg_base(timer_info->timer); // ��ȡ�Ĵ�������ַ |
| 97 | reg_write_32(0, (volatile unsigned int *)(timer_reg_base + LS1C_PWM_HRC)); |
| 98 | reg_write_32(tmp--, (volatile unsigned int *)(timer_reg_base + LS1C_PWM_LRC)); |
| 99 | reg_write_32(0, (volatile unsigned int *)(timer_reg_base + LS1C_PWM_CNTR)); |
| 100 | reg_write_32(ctrl, (volatile unsigned int *)(timer_reg_base + LS1C_PWM_CTRL)); |
| 101 | |
| 102 | return ; |
| 103 | } |
| 104 | |
| 105 | |
| 106 | /* |
nothing calls this directly
no test coverage detected