* ��ʼ��ָ��i2cģ�� * @i2c_info_p ij��i2cģ�����Ϣ */
| 202 | * @i2c_info_p ij��i2cģ�����Ϣ |
| 203 | */ |
| 204 | void i2c_init(ls1c_i2c_info_t *i2c_info_p) |
| 205 | { |
| 206 | void *i2c_base = i2c_get_base(i2c_info_p->I2Cx); |
| 207 | unsigned long i2c_clock = i2c_info_p->clock; |
| 208 | unsigned char ctrl = reg_read_8(i2c_base + LS1C_I2C_CONTROL_OFFSET); |
| 209 | unsigned long prescale = 0; |
| 210 | |
| 211 | /* make sure the device is disabled */ |
| 212 | ctrl = ctrl & ~(LS1C_I2C_CONTROL_EN | LS1C_I2C_CONTROL_IEN); |
| 213 | reg_write_8(ctrl, i2c_base + LS1C_I2C_CONTROL_OFFSET); |
| 214 | |
| 215 | // ����ʱ�� |
| 216 | i2c_clock = MIN(i2c_clock, LS1C_I2C_CLOCK_MAX); // ����������������� |
| 217 | prescale = clk_get_apb_rate(); |
| 218 | prescale = (prescale / (5 * i2c_clock)) - 1; |
| 219 | reg_write_8(prescale & 0xff, i2c_base + LS1C_I2C_PRER_LOW_OFFSET); |
| 220 | reg_write_8(prescale >> 8, i2c_base + LS1C_I2C_PRER_HIGH_OFFSET); |
| 221 | |
| 222 | // ʹ�� |
| 223 | i2c_cmd_iack(i2c_info_p); |
| 224 | ctrl = ctrl | LS1C_I2C_CONTROL_EN; |
| 225 | reg_write_8(ctrl, i2c_base + LS1C_I2C_CONTROL_OFFSET); |
| 226 | |
| 227 | return ; |
| 228 | } |
| 229 | |
| 230 | |
| 231 | /* |
no test coverage detected