| 64 | pwm_enable(&pwm_info); |
| 65 | } |
| 66 | int caclulate_freq(rt_uint32_t XIN, rt_uint32_t PCLK) |
| 67 | { |
| 68 | rt_uint32_t divider_int; |
| 69 | rt_uint32_t needed_pixclk; |
| 70 | rt_uint32_t pll_clk, pix_div; |
| 71 | rt_uint32_t regval; |
| 72 | |
| 73 | |
| 74 | pll_clk = PLL_FREQ; // 读CPU的 PLL及SDRAM 分频系数 |
| 75 | pll_clk =( pll_clk>>8 )& 0xff; |
| 76 | pll_clk = XIN * pll_clk / 4 ; |
| 77 | pix_div = PLL_DIV_PARAM;//读CPU的 CPU/CAMERA/DC 分频系数 |
| 78 | pix_div = (pix_div>>24)&0xff; |
| 79 | rt_kprintf("old pll_clk=%d, pix_div=%d\n", pll_clk, pix_div); |
| 80 | |
| 81 | divider_int = pll_clk/(1000000) *PCLK/1000; |
| 82 | if(divider_int%1000>=500) |
| 83 | divider_int = divider_int/1000+1; |
| 84 | else |
| 85 | divider_int = divider_int/1000; |
| 86 | rt_kprintf("divider_int = %d\n", divider_int); |
| 87 | |
| 88 | /* check whether divisor is too small. */ |
| 89 | if (divider_int < 1) { |
| 90 | rt_kprintf("Warning: clock source is too slow.Try smaller resolution\n"); |
| 91 | divider_int = 1; |
| 92 | } |
| 93 | else if(divider_int > 100) { |
| 94 | rt_kprintf("Warning: clock source is too fast.Try smaller resolution\n"); |
| 95 | divider_int = 100; |
| 96 | } |
| 97 | /* 配置分频寄存器 */ |
| 98 | { |
| 99 | rt_uint32_t regval = 0; |
| 100 | regval = PLL_DIV_PARAM; |
| 101 | /*首先需要把分频使能位清零 */ |
| 102 | regval &= ~0x80000030; //PIX_DIV_VALID PIX_SEL 置0 |
| 103 | regval &= ~(0x3f<<24); //PIX_DIV 清零 |
| 104 | regval |= divider_int << 24; |
| 105 | PLL_DIV_PARAM = regval; |
| 106 | regval |= 0x80000030; //PIX_DIV_VALID PIX_SEL 置1 |
| 107 | PLL_DIV_PARAM = regval; |
| 108 | } |
| 109 | rt_kprintf("new PLL_FREQ=0x%x, PLL_DIV_PARAM=0x%x\n", PLL_FREQ, PLL_DIV_PARAM); |
| 110 | rt_thread_delay(10); |
| 111 | return 0; |
| 112 | } |
| 113 | |
| 114 | static rt_err_t rt_dc_init(rt_device_t dev) |
| 115 | { |
no test coverage detected