| 875 | } |
| 876 | |
| 877 | static int hpm_uart_dma_config(struct rt_serial_device *serial, void *arg) |
| 878 | { |
| 879 | rt_ubase_t ctrl_arg = (rt_ubase_t) arg; |
| 880 | struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; |
| 881 | struct rt_serial_rx_fifo *rx_fifo; |
| 882 | dma_mgr_chn_conf_t chg_config; |
| 883 | dma_mgr_get_default_chn_config(&chg_config); |
| 884 | if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) { |
| 885 | rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; |
| 886 | chg_config.dst_addr_ctrl = DMA_MGR_ADDRESS_CONTROL_INCREMENT; |
| 887 | chg_config.dst_mode = DMA_MGR_HANDSHAKE_MODE_NORMAL; |
| 888 | chg_config.dst_width = DMA_TRANSFER_WIDTH_BYTE; |
| 889 | chg_config.en_dmamux = true; |
| 890 | chg_config.dmamux_src = uart->rx_dma_mux; |
| 891 | chg_config.src_addr = (uint32_t)&(uart->uart_base->RBR); |
| 892 | chg_config.src_addr_ctrl = DMA_MGR_ADDRESS_CONTROL_FIXED; |
| 893 | chg_config.src_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; |
| 894 | chg_config.src_width = DMA_TRANSFER_WIDTH_BYTE; |
| 895 | |
| 896 | #if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) |
| 897 | chg_config.dst_addr = (uint32_t)uart->rx_idle_tmp_buffer; |
| 898 | chg_config.size_in_byte = sizeof(uart->rx_idle_tmp_buffer); |
| 899 | #else |
| 900 | chg_config.dst_addr = (uint32_t)rx_fifo->rb.buffer_ptr; |
| 901 | chg_config.size_in_byte = serial->config.rx_bufsz; |
| 902 | #endif |
| 903 | if (status_success != dma_mgr_setup_channel(&uart->rx_chn_ctx.resource, &chg_config)) { |
| 904 | return -RT_ERROR; |
| 905 | } |
| 906 | dma_mgr_enable_channel(&uart->rx_chn_ctx.resource); |
| 907 | dma_mgr_enable_chn_irq(&uart->rx_chn_ctx.resource, DMA_MGR_INTERRUPT_MASK_TC); |
| 908 | dma_mgr_enable_dma_irq_with_priority(&uart->rx_chn_ctx.resource, 1); |
| 909 | hpm_uart_dma_register_channel(serial, false, uart_rx_done, RT_NULL, RT_NULL); |
| 910 | #if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) |
| 911 | intc_m_enable_irq_with_priority(uart->irq_num, uart->irq_priority); |
| 912 | #endif |
| 913 | } else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) { |
| 914 | chg_config.src_addr_ctrl = DMA_MGR_ADDRESS_CONTROL_INCREMENT; |
| 915 | chg_config.src_mode = DMA_MGR_HANDSHAKE_MODE_NORMAL; |
| 916 | chg_config.src_width = DMA_TRANSFER_WIDTH_BYTE; |
| 917 | chg_config.dst_addr = (uint32_t)&uart->uart_base->THR; |
| 918 | chg_config.dst_addr_ctrl = DMA_MGR_ADDRESS_CONTROL_FIXED; |
| 919 | chg_config.dst_mode = DMA_MGR_HANDSHAKE_MODE_HANDSHAKE; |
| 920 | chg_config.dst_width = DMA_TRANSFER_WIDTH_BYTE; |
| 921 | chg_config.en_dmamux = true; |
| 922 | chg_config.dmamux_src = uart->tx_dma_mux; |
| 923 | if (status_success != dma_mgr_setup_channel(&uart->tx_chn_ctx.resource, &chg_config)) { |
| 924 | return -RT_ERROR; |
| 925 | } |
| 926 | dma_mgr_enable_chn_irq(&uart->tx_chn_ctx.resource, DMA_MGR_INTERRUPT_MASK_TC); |
| 927 | dma_mgr_enable_dma_irq_with_priority(&uart->tx_chn_ctx.resource, 1); |
| 928 | } |
| 929 | return RT_EOK; |
| 930 | } |
| 931 | |
| 932 | static void hpm_uart_receive_dma_next(struct rt_serial_device *serial) |
| 933 | { |
no test coverage detected