| 45 | } |
| 46 | |
| 47 | void FCache_cpuDcacheClean(void *addr, ft_base_t size) |
| 48 | { |
| 49 | u32 lineSize = FCache_cacheLineSize(); |
| 50 | u32 startAddr = (u32)addr; |
| 51 | u32 endAddr = (u32)addr + size + lineSize - 1; |
| 52 | |
| 53 | asm volatile("dmb" :: |
| 54 | : "memory"); |
| 55 | |
| 56 | startAddr &= ~(lineSize - 1); |
| 57 | endAddr &= ~(lineSize - 1); |
| 58 | |
| 59 | while (startAddr < endAddr) |
| 60 | { |
| 61 | asm volatile("mcr p15, 0, %0, c7, c10, 1" ::"r"(startAddr)); /* dccmvac */ |
| 62 | startAddr += lineSize; |
| 63 | } |
| 64 | |
| 65 | asm volatile("dsb" :: |
| 66 | : "memory"); |
| 67 | } |
| 68 | |
| 69 | void FCache_cpuIcacheInvalidate(void *addr, ft_base_t size) |
| 70 | { |
no test coverage detected