| 264 | } |
| 265 | |
| 266 | ft_error_t FSdCtrl_WaitWriteDataEnd(FT_INOUT FtsdCtrl_t *pFtsdCtrl, |
| 267 | FT_IN pFtsdCtrl_delayTimer_t pDelayTimer_fun, |
| 268 | FT_IN u32 blkNum) |
| 269 | { |
| 270 | u32 status; |
| 271 | u32 statusMask; |
| 272 | ft_error_t ret; |
| 273 | s32 timeout = 1000; |
| 274 | FSdCtrl_Config_t *pConfig; |
| 275 | |
| 276 | Ft_assertNonvoid(FT_NULL != pFtsdCtrl); |
| 277 | pConfig = &pFtsdCtrl->config; |
| 278 | |
| 279 | if (pConfig->workMode & FTSDCTRL_DATA_WRITE_IRQ_MASK) |
| 280 | { |
| 281 | /* enter irq mode */ |
| 282 | if (NULL == pFtsdCtrl->writeWaitCallback) |
| 283 | { |
| 284 | return FTSDC_INVALID_PARAM; |
| 285 | } |
| 286 | |
| 287 | ret = pFtsdCtrl->writeWaitCallback(pFtsdCtrl); |
| 288 | if (FTSDC_SUCCESS != ret) |
| 289 | { |
| 290 | return FTSDC_EILSEQ; |
| 291 | } |
| 292 | } |
| 293 | else |
| 294 | { |
| 295 | /* wait for DMA-error or DMA-finished status */ |
| 296 | statusMask = BD_ISR_REG_DAIS | BD_ISR_REG_TRS; |
| 297 | do |
| 298 | { |
| 299 | status = (Ft_in32(pConfig->baseAddress + BD_ISR_REG) & statusMask); |
| 300 | pDelayTimer_fun(1); |
| 301 | timeout--; |
| 302 | } while ((!status) && timeout); |
| 303 | |
| 304 | if (status & BD_ISR_REG_DAIS) |
| 305 | { |
| 306 | if (status & (BD_ISR_REG_TRE | BD_ISR_REG_NRCRC | BD_ISR_REG_CMDE)) |
| 307 | { |
| 308 | return FTSDC_EILSEQ; |
| 309 | } |
| 310 | else if (!timeout) |
| 311 | { |
| 312 | return FTSDC_TIMEOUT; |
| 313 | } |
| 314 | } |
| 315 | } |
| 316 | |
| 317 | /* multi block needs MMC_STOP_TRANSMISSION to stop process*/ |
| 318 | if (blkNum > 1) |
| 319 | { |
| 320 | return FsdCtrl_privateSendCmd(pFtsdCtrl, pDelayTimer_fun, 12, CMD_SETTING_RTS(2), 0); |
| 321 | } |
| 322 | |
| 323 | return FTSDC_SUCCESS; |
no test coverage detected