/ * @brief * Initialize Ethernet device * * @details * * @note * * @param[in] dev * Pointer to device descriptor * * @return * Error code ******************************************************************************/
| 424 | * Error code |
| 425 | ******************************************************************************/ |
| 426 | static rt_err_t efm_eth_init(rt_device_t dev) |
| 427 | { |
| 428 | rt_uint16_t reg_phy; |
| 429 | rt_uint8_t data; |
| 430 | |
| 431 | /* Reset chip select */ |
| 432 | efm_eth_cs(0); |
| 433 | /* Software reset */ |
| 434 | efm_eth_sendCmd(ENC28J60_SOFT_RESET, EFM32_NO_DATA, EFM32_NO_POINTER); |
| 435 | /* Waiting for at least 1 ms (Errata 2) */ |
| 436 | rt_thread_delay(ETH_PERIOD_WAIT_INIT); |
| 437 | ethNxtPkt = RXSTART_INIT; |
| 438 | ethBank = 0; |
| 439 | |
| 440 | /* Init RX buffer */ |
| 441 | efm_eth_writeReg(ERXSTL, RXSTART_INIT & 0xFF); |
| 442 | efm_eth_writeReg(ERXSTH, RXSTART_INIT >> 8); |
| 443 | efm_eth_writeReg(ERXNDL, RXSTOP_INIT & 0xFF); |
| 444 | efm_eth_writeReg(ERXNDH, RXSTOP_INIT >> 8); |
| 445 | efm_eth_writeReg(ERXRDPTL, RXSTOP_INIT & 0xFF); |
| 446 | efm_eth_writeReg(ERXRDPTH, RXSTOP_INIT >> 8); |
| 447 | |
| 448 | /* Init TX buffer */ |
| 449 | efm_eth_writeReg(ETXSTL, TXSTART_INIT & 0xFF); |
| 450 | efm_eth_writeReg(ETXSTH, TXSTART_INIT >> 8); |
| 451 | efm_eth_writeReg(ETXNDL, TXSTOP_INIT & 0xFF); |
| 452 | efm_eth_writeReg(ETXNDH, TXSTOP_INIT >> 8); |
| 453 | efm_eth_writeReg(EWRPTL, TXSTART_INIT & 0xFF); |
| 454 | efm_eth_writeReg(EWRPTH, TXSTART_INIT >> 8); |
| 455 | |
| 456 | /* Init RX filters */ |
| 457 | /* For broadcast packets we allow only ARP packtets |
| 458 | All other packets should be unicast only for our mac (MAADR) |
| 459 | |
| 460 | The pattern to match on is therefore |
| 461 | Type ETH.DST |
| 462 | ARP BROADCAST |
| 463 | 06 08 -- -- -- -- -- -- ff ff ff ff ff ff |
| 464 | These poitions are: 11 0000 0011 1111 in binary and 30 3f in hex |
| 465 | Checksum for theses bytes is: f7 f9 */ |
| 466 | efm_eth_writeReg(EPMM0, 0x3f); |
| 467 | efm_eth_writeReg(EPMM1, 0x30); |
| 468 | efm_eth_writeReg(EPMCSL, 0xf9); |
| 469 | efm_eth_writeReg(EPMCSH, 0xf7); |
| 470 | efm_eth_writeReg(ERXFCON, ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_PMEN); |
| 471 | //efm_eth_writeReg(ERXFCON, ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN); |
| 472 | /* Waiting For OST: The OST does not expire until 7500 OSC1 clock cycles (300 uS) |
| 473 | pass after Power-on Reset or wake-up from Power-Down mode occurs */ |
| 474 | |
| 475 | /* Init MAC */ |
| 476 | /* Enable RX, IEEE defined flow control */ |
| 477 | efm_eth_writeReg(MACON1, MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS); |
| 478 | /* Enable padding to 60 bytes, CRC and frame length status reporting */ |
| 479 | #if defined(ETH_HALF_DUPLEX) |
| 480 | efm_eth_writeReg(MACON3, MACON3_PADCFG0 | MACON3_TXCRCEN | MACON3_FRMLNEN); |
| 481 | efm_eth_writeReg(MACON4, MACON4_DEFER); |
| 482 | #else |
| 483 | efm_eth_writeReg(MACON3, \ |
nothing calls this directly
no test coverage detected