/ * @brief * Configure DMA for ADC * * @details * * @note * * @param[in] adc_device * Pointer to ADC registers base address * * @param[in] mode * ADC mode * * @param[in] channel * DMA channel ******************************************************************************/
| 211 | * DMA channel |
| 212 | ******************************************************************************/ |
| 213 | void efm32_adc_cfg_dma( |
| 214 | ADC_TypeDef *adc_device, |
| 215 | rt_uint8_t mode, |
| 216 | rt_uint8_t channel) |
| 217 | { |
| 218 | DMA_CfgChannel_TypeDef chnlCfg; |
| 219 | DMA_CfgDescr_TypeDef descrCfg; |
| 220 | |
| 221 | if (channel == (rt_uint8_t)EFM32_NO_DMA) |
| 222 | { |
| 223 | return; |
| 224 | } |
| 225 | |
| 226 | /* Set up DMA channel */ |
| 227 | chnlCfg.highPri = false; |
| 228 | chnlCfg.enableInt = false; |
| 229 | if (adc_device == ADC0) |
| 230 | { |
| 231 | switch (mode & ADC_MASK_MODE) |
| 232 | { |
| 233 | case ADC_MODE_SINGLE: |
| 234 | chnlCfg.select = DMAREQ_ADC0_SINGLE; |
| 235 | break; |
| 236 | |
| 237 | case ADC_MODE_SCAN: |
| 238 | chnlCfg.select = DMAREQ_ADC0_SCAN; |
| 239 | break; |
| 240 | |
| 241 | default: |
| 242 | return; |
| 243 | } |
| 244 | } |
| 245 | else |
| 246 | { |
| 247 | // TODO: Any other channel? |
| 248 | return; |
| 249 | } |
| 250 | chnlCfg.cb = RT_NULL; |
| 251 | DMA_CfgChannel((rt_uint32_t)channel, &chnlCfg); |
| 252 | |
| 253 | /* Setting up DMA channel descriptor */ |
| 254 | descrCfg.dstInc = dmaDataInc4; |
| 255 | descrCfg.srcInc = dmaDataIncNone; |
| 256 | descrCfg.size = dmaDataSize4; |
| 257 | descrCfg.arbRate = dmaArbitrate1; |
| 258 | descrCfg.hprot = 0; |
| 259 | DMA_CfgDescr((rt_uint32_t)channel, true, &descrCfg); |
| 260 | } |
| 261 | |
| 262 | /***************************************************************************//** |
| 263 | * @brief |
no test coverage detected