/ * @brief * Get the cause of the last reset. * * @details * In order to be useful, the reset cause must be cleared by SW before a new * reset occurs, otherwise reset causes may accumulate. See * RMU_ResetCauseClear(). This function call will return the main cause for * reset, which can be a bit mask (several causes), and clear away "noise". * * @return * The reset cause, a b
| 122 | * @li RMU_RSTCAUSE_BUMODERST - System has been in Backup mode |
| 123 | ******************************************************************************/ |
| 124 | uint32_t RMU_ResetCauseGet(void) |
| 125 | { |
| 126 | uint32_t ret = RMU->RSTCAUSE; |
| 127 | |
| 128 | /* Inspect and decode bits. The decoding must be done in correct order, */ |
| 129 | /* since some reset causes may trigger other reset causes due to internal */ |
| 130 | /* design. We are only interested in the main cause. */ |
| 131 | #if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) |
| 132 | /* Clear "stray" bits if EM4 bit is set, they will always be active */ |
| 133 | if (ret & RMU_RSTCAUSE_EM4RST) |
| 134 | { |
| 135 | ret &= ~(RMU_RSTCAUSE_BODREGRST| |
| 136 | RMU_RSTCAUSE_BODUNREGRST| |
| 137 | RMU_RSTCAUSE_LOCKUPRST| |
| 138 | RMU_RSTCAUSE_SYSREQRST); |
| 139 | } |
| 140 | #endif |
| 141 | if (ret & RMU_RSTCAUSE_PORST) |
| 142 | { |
| 143 | ret = RMU_RSTCAUSE_PORST; |
| 144 | } |
| 145 | else if ((ret & 0x83) == RMU_RSTCAUSE_BODUNREGRST) |
| 146 | { |
| 147 | ret = RMU_RSTCAUSE_BODUNREGRST; |
| 148 | } |
| 149 | else if ((ret & 0x1f) == RMU_RSTCAUSE_BODREGRST) |
| 150 | { |
| 151 | ret = RMU_RSTCAUSE_BODREGRST; |
| 152 | } |
| 153 | /* Both external and watchdog reset may occur at the same time */ |
| 154 | else if ((ret & 0x1b) & (RMU_RSTCAUSE_EXTRST | RMU_RSTCAUSE_WDOGRST)) |
| 155 | { |
| 156 | ret &= RMU_RSTCAUSE_EXTRST | RMU_RSTCAUSE_WDOGRST; |
| 157 | } |
| 158 | /* Both lockup and system reset may occur at the same time */ |
| 159 | else if ((ret & 0x7ff) & (RMU_RSTCAUSE_LOCKUPRST | RMU_RSTCAUSE_SYSREQRST)) |
| 160 | { |
| 161 | ret &= RMU_RSTCAUSE_LOCKUPRST | RMU_RSTCAUSE_SYSREQRST; |
| 162 | } |
| 163 | /* EM4 wake up and pin retention support */ |
| 164 | #if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) |
| 165 | else if (ret & RMU_RSTCAUSE_BODAVDD0) |
| 166 | { |
| 167 | ret = RMU_RSTCAUSE_BODAVDD0; |
| 168 | } |
| 169 | else if (ret & RMU_RSTCAUSE_BODAVDD1) |
| 170 | { |
| 171 | ret = RMU_RSTCAUSE_BODAVDD1; |
| 172 | } |
| 173 | else if (ret & (RMU_RSTCAUSE_EM4WURST|RMU_RSTCAUSE_EM4RST)) |
| 174 | { |
| 175 | ret &= (RMU_RSTCAUSE_EM4WURST| |
| 176 | #if defined(_EFM32_GIANT_FAMILY) |
| 177 | RMU_RSTCAUSE_BUMODERST| |
| 178 | #endif |
| 179 | RMU_RSTCAUSE_EM4RST); |
| 180 | } |
| 181 | else if (ret & (RMU_RSTCAUSE_EM4RST|RMU_RSTCAUSE_EXTRST)) |