/ * @brief * Configure timing values of write bus accesses * * @param[in] setupCycles * Number of clock cycles for address setup before WEn is asserted * * @param[in] strobeCycles * Number of cycles WEn is held active. If set to 0, 1 cycle is inserted by HW * * @param[in] holdCycles * Number of cycles CSn is held active after the WEn is deasserted *******************************
| 507 | * Number of cycles CSn is held active after the WEn is deasserted |
| 508 | ******************************************************************************/ |
| 509 | void EBI_WriteTimingSet(int setupCycles, int strobeCycles, int holdCycles) |
| 510 | { |
| 511 | uint32_t writeTiming; |
| 512 | |
| 513 | /* Check that timings are within limits */ |
| 514 | EFM_ASSERT(setupCycles < 4); |
| 515 | EFM_ASSERT(strobeCycles < 16); |
| 516 | EFM_ASSERT(holdCycles < 4); |
| 517 | |
| 518 | /* Configure timing values */ |
| 519 | writeTiming = (setupCycles << _EBI_WRTIMING_WRSETUP_SHIFT) | |
| 520 | (strobeCycles << _EBI_WRTIMING_WRSTRB_SHIFT) | |
| 521 | (holdCycles << _EBI_WRTIMING_WRHOLD_SHIFT); |
| 522 | |
| 523 | EBI->WRTIMING = (EBI->WRTIMING & |
| 524 | ~(_EBI_WRTIMING_WRSETUP_MASK | |
| 525 | _EBI_WRTIMING_WRSTRB_MASK | |
| 526 | _EBI_WRTIMING_WRHOLD_MASK)) | writeTiming; |
| 527 | } |
| 528 | |
| 529 | |
| 530 | /***************************************************************************//** |