/ * @brief * Configure timing values of write bus accesses * * @param[in] banks * Mask of memory bank(s) to configure write timing for * * @param[in] setupCycles * Number of clock cycles for address setup before WEn is asserted * * @param[in] strobeCycles * Number of cycles WEn is held active. If set to 0, 1 cycle is inserted by HW * * @param[in] holdCycles * Number of cycle
| 881 | * Number of cycles CSn is held active after the WEn is deasserted |
| 882 | ******************************************************************************/ |
| 883 | void EBI_BankWriteTimingSet(uint32_t banks, int setupCycles, int strobeCycles, int holdCycles) |
| 884 | { |
| 885 | uint32_t writeTiming; |
| 886 | |
| 887 | /* Verify only valid banks are used */ |
| 888 | EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0); |
| 889 | |
| 890 | /* Check that timings are within limits */ |
| 891 | EFM_ASSERT(setupCycles < 4); |
| 892 | EFM_ASSERT(strobeCycles < 64); |
| 893 | EFM_ASSERT(holdCycles < 4); |
| 894 | |
| 895 | /* Configure timing values */ |
| 896 | writeTiming = (setupCycles << _EBI_WRTIMING_WRSETUP_SHIFT) | |
| 897 | (strobeCycles << _EBI_WRTIMING_WRSTRB_SHIFT) | |
| 898 | (holdCycles << _EBI_WRTIMING_WRHOLD_SHIFT); |
| 899 | |
| 900 | if (banks & EBI_BANK0) |
| 901 | { |
| 902 | EBI->WRTIMING = (EBI->WRTIMING & |
| 903 | ~(_EBI_WRTIMING_WRSETUP_MASK | |
| 904 | _EBI_WRTIMING_WRSTRB_MASK | |
| 905 | _EBI_WRTIMING_WRHOLD_MASK)) | writeTiming; |
| 906 | } |
| 907 | if (banks & EBI_BANK1) |
| 908 | { |
| 909 | EBI->WRTIMING1 = (EBI->WRTIMING1 & |
| 910 | ~(_EBI_WRTIMING1_WRSETUP_MASK | |
| 911 | _EBI_WRTIMING1_WRSTRB_MASK | |
| 912 | _EBI_WRTIMING1_WRHOLD_MASK)) | writeTiming; |
| 913 | } |
| 914 | if (banks & EBI_BANK2) |
| 915 | { |
| 916 | EBI->WRTIMING2 = (EBI->WRTIMING2 & |
| 917 | ~(_EBI_WRTIMING2_WRSETUP_MASK | |
| 918 | _EBI_WRTIMING2_WRSTRB_MASK | |
| 919 | _EBI_WRTIMING2_WRHOLD_MASK)) | writeTiming; |
| 920 | } |
| 921 | if (banks & EBI_BANK3) |
| 922 | { |
| 923 | EBI->WRTIMING3 = (EBI->WRTIMING3 & |
| 924 | ~(_EBI_WRTIMING3_WRSETUP_MASK | |
| 925 | _EBI_WRTIMING3_WRSTRB_MASK | |
| 926 | _EBI_WRTIMING3_WRHOLD_MASK)) | writeTiming; |
| 927 | } |
| 928 | } |
| 929 | |
| 930 | |
| 931 | /***************************************************************************//** |