/ * @brief * Chip initialization routine for revision errata workarounds * * This init function will configure the EFM32 device to a state where it is * as similar as later revisions as possible, to improve software compatibility * with newer parts. See the device specific errata for details. *****************************************************************************/
| 60 | * with newer parts. See the device specific errata for details. |
| 61 | *****************************************************************************/ |
| 62 | __STATIC_INLINE void CHIP_Init(void) |
| 63 | { |
| 64 | /* Currently only run time changes for Gecko devices */ |
| 65 | #if defined(_EFM32_GECKO_FAMILY) |
| 66 | uint32_t rev; |
| 67 | SYSTEM_ChipRevision_TypeDef chipRev; |
| 68 | volatile uint32_t *reg; |
| 69 | |
| 70 | rev = *(volatile uint32_t *)(0x0FE081FC); |
| 71 | /* Engineering Sample calibration setup */ |
| 72 | if ((rev >> 24) == 0) |
| 73 | { |
| 74 | reg = (volatile uint32_t *)0x400CA00C; |
| 75 | *reg &= ~(0x70UL); |
| 76 | /* DREG */ |
| 77 | reg = (volatile uint32_t *)0x400C6020; |
| 78 | *reg &= ~(0xE0000000UL); |
| 79 | *reg |= ~(7UL << 25); |
| 80 | } |
| 81 | if ((rev >> 24) <= 3) |
| 82 | { |
| 83 | /* DREG */ |
| 84 | reg = (volatile uint32_t *)0x400C6020; |
| 85 | *reg &= ~(0x00001F80UL); |
| 86 | /* Update CMU reset values */ |
| 87 | reg = (volatile uint32_t *)0x400C8040; |
| 88 | *reg = 0; |
| 89 | reg = (volatile uint32_t *)0x400C8044; |
| 90 | *reg = 0; |
| 91 | reg = (volatile uint32_t *)0x400C8058; |
| 92 | *reg = 0; |
| 93 | reg = (volatile uint32_t *)0x400C8060; |
| 94 | *reg = 0; |
| 95 | reg = (volatile uint32_t *)0x400C8078; |
| 96 | *reg = 0; |
| 97 | } |
| 98 | |
| 99 | SYSTEM_ChipRevisionGet(&chipRev); |
| 100 | if (chipRev.major == 0x01) |
| 101 | { |
| 102 | /* Rev A errata handling for EM2/3. Must enable DMA clock in order for EM2/3 */ |
| 103 | /* to work. This will be fixed in later chip revisions, so only do for rev A. */ |
| 104 | if (chipRev.minor == 00) |
| 105 | { |
| 106 | reg = (volatile uint32_t *)0x400C8040; |
| 107 | *reg |= 0x2; |
| 108 | } |
| 109 | |
| 110 | /* Rev A+B errata handling for I2C when using EM2/3. USART0 clock must be enabled */ |
| 111 | /* after waking up from EM2/EM3 in order for I2C to work. This will be fixed in */ |
| 112 | /* later chip revisions, so only do for rev A+B. */ |
| 113 | if (chipRev.minor <= 0x01) |
| 114 | { |
| 115 | reg = (volatile uint32_t *)0x400C8044; |
| 116 | *reg |= 0x1; |
| 117 | } |
| 118 | } |
| 119 | /* Ensure correct ADC/DAC calibration value */ |
no test coverage detected