* Interface to control the chip select signal */
| 218 | * Interface to control the chip select signal |
| 219 | */ |
| 220 | static void davinci_spi_chipselect(struct rt_spi_device *spi, int value) |
| 221 | { |
| 222 | struct davinci_spi *dspi; |
| 223 | u8 chip_sel = (u8)spi->parent.user_data; |
| 224 | u16 spidat1 = CS_DEFAULT; |
| 225 | bool gpio_chipsel = RT_FALSE; |
| 226 | |
| 227 | dspi = spi->bus->parent.user_data; |
| 228 | |
| 229 | if (chip_sel < SPI_MAX_CHIPSELECT && |
| 230 | dspi->chip_sel[chip_sel] != SPI_INTERN_CS) |
| 231 | gpio_chipsel = RT_TRUE; |
| 232 | |
| 233 | /* |
| 234 | * Board specific chip select logic decides the polarity and cs |
| 235 | * line for the controller |
| 236 | */ |
| 237 | if (gpio_chipsel) { |
| 238 | if (value == 0) |
| 239 | gpio_set_value(dspi->chip_sel[chip_sel], 0); |
| 240 | else |
| 241 | gpio_set_value(dspi->chip_sel[chip_sel], 1); |
| 242 | } else { |
| 243 | spidat1 = readw(dspi->base + SPIDAT1 + 2); |
| 244 | if (value == 0) { |
| 245 | spidat1 |= SPIDAT1_CSHOLD_MASK; |
| 246 | spidat1 &= ~(0x1 << chip_sel); |
| 247 | } else { |
| 248 | spidat1 &= ~SPIDAT1_CSHOLD_MASK; |
| 249 | spidat1 |= 0x03; |
| 250 | } |
| 251 | rt_kprintf("0x%04x\n", spidat1); |
| 252 | |
| 253 | writew(spidat1, dspi->base + SPIDAT1 + 2); |
| 254 | } |
| 255 | } |
| 256 | |
| 257 | /** |
| 258 | * davinci_spi_get_prescale - Calculates the correct prescale value |
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