| 215 | } |
| 216 | |
| 217 | static int32_t designware_eth_init(eth_mac_handle_t handle) |
| 218 | { |
| 219 | gmac_dev_t *mac_dev = (gmac_dev_t *)handle; |
| 220 | struct dw_gmac_mac_regs *mac_reg = mac_dev->priv->mac_regs_p; |
| 221 | struct dw_gmac_dma_regs *dma_reg = mac_dev->priv->dma_regs_p; |
| 222 | |
| 223 | uint32_t start; |
| 224 | |
| 225 | dma_reg->busmode |= CVI_DMAMAC_SRST; |
| 226 | |
| 227 | start = rt_tick_get_millisecond(); |
| 228 | while (dma_reg->busmode & CVI_DMAMAC_SRST) { |
| 229 | if ((rt_tick_get_millisecond() - start) >= CVI_CONFIG_MACRESET_TIMEOUT) { |
| 230 | rt_kprintf("DMA reset timeout\n"); |
| 231 | return -ETIMEDOUT; |
| 232 | } |
| 233 | |
| 234 | rt_thread_mdelay(100); |
| 235 | }; |
| 236 | |
| 237 | /* |
| 238 | * Soft reset above clears HW address registers. |
| 239 | * So we have to set it here once again. |
| 240 | */ |
| 241 | // designware_read_hwaddr(handle); |
| 242 | // designware_write_hwaddr(handle); |
| 243 | |
| 244 | rx_descs_init(handle); |
| 245 | tx_descs_init(handle); |
| 246 | |
| 247 | dma_reg->busmode = (CVI_FIXEDBURST | CVI_PRIORXTX_41 | CVI_DMA_PBL); |
| 248 | |
| 249 | // mac_reg->framefilt = 0x10; |
| 250 | // mac_reg->flowcontrol = 0x8; |
| 251 | // dma_reg->wdtforri = 0xff; |
| 252 | // dma_reg->axibus = 0x0012100F; |
| 253 | |
| 254 | #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE |
| 255 | dma_reg->opmode |= (CVI_FLUSHTXFIFO | CVI_STOREFORWARD); |
| 256 | #else |
| 257 | dma_reg->opmode |= CVI_FLUSHTXFIFO; |
| 258 | #endif |
| 259 | |
| 260 | dma_reg->opmode |= (CVI_RXSTART | CVI_TXSTART); |
| 261 | dma_reg->opmode = 0x2202906; |
| 262 | dma_reg->busmode = 0x3900800; |
| 263 | mac_reg->conf = 0x41cc00; |
| 264 | dma_reg->intenable = 0x10040; |
| 265 | |
| 266 | #ifdef CONFIG_DW_AXI_BURST_LEN |
| 267 | dma_reg->axibus = (CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1); |
| 268 | #endif |
| 269 | |
| 270 | /* Start up the PHY */ |
| 271 | /* adjust link */ |
| 272 | return 0; |
| 273 | } |
| 274 |
no test coverage detected