* @brief phy clock config */
| 144 | * @brief phy clock config |
| 145 | */ |
| 146 | static void phy_clock_config(void) |
| 147 | { |
| 148 | #if (CRYSTAL_ON_PHY == 0) |
| 149 | /* if CRYSTAL_NO_PHY, output clock with pa8 of mcu */ |
| 150 | gpio_init_type gpio_init_struct; |
| 151 | |
| 152 | crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE); |
| 153 | |
| 154 | gpio_default_para_init(&gpio_init_struct); |
| 155 | gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; |
| 156 | gpio_init_struct.gpio_mode = GPIO_MODE_MUX; |
| 157 | gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; |
| 158 | gpio_init_struct.gpio_pull = GPIO_PULL_NONE; |
| 159 | gpio_init_struct.gpio_pins = GPIO_PINS_8; |
| 160 | gpio_init(GPIOA, &gpio_init_struct); |
| 161 | |
| 162 | /* 9162 clkout output 25 mhz */ |
| 163 | /* 83848 clkout output 50 mhz */ |
| 164 | #if defined (SOC_SERIES_AT32F407) |
| 165 | crm_clock_out_set(CRM_CLKOUT_SCLK); |
| 166 | #if defined (PHY_USING_DM9162) || defined (PHY_USING_LAN8720) || \ |
| 167 | defined (PHY_USING_YT8512) |
| 168 | crm_clkout_div_set(CRM_CLKOUT_DIV_8); |
| 169 | #elif defined (PHY_USING_DP83848) |
| 170 | crm_clkout_div_set(CRM_CLKOUT_DIV_4); |
| 171 | #endif |
| 172 | #endif |
| 173 | |
| 174 | #if defined (SOC_SERIES_AT32F437) |
| 175 | crm_clock_out1_set(CRM_CLKOUT1_PLL); |
| 176 | #if defined (PHY_USING_DM9162) || defined (PHY_USING_LAN8720) || \ |
| 177 | defined (PHY_USING_YT8512) |
| 178 | crm_clkout_div_set(CRM_CLKOUT_INDEX_1, CRM_CLKOUT_DIV1_5, CRM_CLKOUT_DIV2_2); |
| 179 | #elif defined (PHY_USING_DP83848) |
| 180 | crm_clkout_div_set(CRM_CLKOUT_INDEX_1, CRM_CLKOUT_DIV1_5, CRM_CLKOUT_DIV2_1); |
| 181 | #endif |
| 182 | #endif |
| 183 | #endif |
| 184 | } |
| 185 | |
| 186 | /** |
| 187 | * @brief reset phy register |
no test coverage detected