| 721 | } |
| 722 | |
| 723 | static rt_ssize_t _uart_transmit(struct rt_serial_device *serial, |
| 724 | rt_uint8_t *buf, rt_size_t size, rt_uint32_t tx_flag) |
| 725 | { |
| 726 | struct sunxi_uart *uart; |
| 727 | size_t uart_base; |
| 728 | |
| 729 | uart = serial->parent.user_data; |
| 730 | uart_base = SUNXI_UART0_BASE + uart->uart_port * 0x400; |
| 731 | |
| 732 | if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX) |
| 733 | { |
| 734 | uint32_t remain = size; |
| 735 | |
| 736 | while (remain) |
| 737 | { |
| 738 | uint32_t write_count = 0; |
| 739 | |
| 740 | while (remain && (hal_readl(uart_base + UART_USR) & UART_USR_TFNF)) |
| 741 | { |
| 742 | rt_uint8_t c = *buf++; |
| 743 | hal_writeb(c, uart_base + UART_THR); |
| 744 | remain--; |
| 745 | write_count++; |
| 746 | } |
| 747 | |
| 748 | while (write_count) |
| 749 | { |
| 750 | if (hal_readl(uart_base + UART_LSR) & UART_LSR_TEMT) |
| 751 | { |
| 752 | break; |
| 753 | } |
| 754 | |
| 755 | rt_completion_init(&(uart->tx_fifo_empty)); |
| 756 | uart_set_isr(uart->uart_port, 1, UART_IER_THRI); |
| 757 | |
| 758 | rt_err_t result = rt_completion_wait(&(uart->tx_fifo_empty), 100); // TODO: timeout calc by baud-rate. |
| 759 | if (result == RT_EOK) |
| 760 | { |
| 761 | break; |
| 762 | } |
| 763 | } |
| 764 | } |
| 765 | |
| 766 | /* last byte, must wait TEMT(transmitter Empty). TODO: need delay? */ |
| 767 | while (1) |
| 768 | { |
| 769 | if (hal_readl(uart_base + UART_LSR) & UART_LSR_TEMT) |
| 770 | { |
| 771 | break; |
| 772 | } |
| 773 | } |
| 774 | |
| 775 | { |
| 776 | struct rt_serial_tx_fifo *tx_fifo = RT_NULL; |
| 777 | tx_fifo = (struct rt_serial_tx_fifo *)serial->serial_tx; |
| 778 | tx_fifo->activated = RT_FALSE; |
| 779 | rt_completion_done(&(tx_fifo->tx_cpt)); |
| 780 | } |
nothing calls this directly
no test coverage detected