* @brief Handle ADD10 flag for Master * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration informati

* @brief Handle ADDR flag for Master * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration informatio

* @brief Handle SB flag for Master * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information

* @brief Handle BTF flag for Slave receiver * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration inf

* @brief Handle RXNE flag for Slave * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information

* @brief Handle BTF flag for Slave transmitter * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration

* @brief Handle TXE flag for Slave * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information

* @brief Handle ADD flag for Slave * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information

* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for I2C module * @retval None */

* @brief Handle STOPF flag for Slave * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration informatio

* @brief This function handles I2C Communication Timeout for specific usage of STOP flag. * @param hi2c Pointer to a I2C_HandleTypeDef structure t

* @brief This function handles I2C Communication Timeout for specific usage of STOP request through Interrupt. * @param hi2c Pointer to a I2C_Hand

* @brief Receive an amount of data in non-blocking mode with Interrupt * @param hi2s pointer to a I2S_HandleTypeDef structure that contains *

* @brief Transmit an amount of data in non-blocking mode with Interrupt * @param hi2s pointer to a I2S_HandleTypeDef structure that contains *

* @brief Configure the TIMx input channel 1. * @param TIMx Timer Instance * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 con

* @brief Configure the TIMx input channel 2. * @param TIMx Timer Instance * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 con

* @brief Configure the TIMx input channel 3. * @param TIMx Timer Instance * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 con

* @brief Configure the TIMx input channel 4. * @param TIMx Timer Instance * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 con

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* @brief Wraps up transmission in non blocking mode. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * th

* @brief Initialize the callbacks to their default values. * @param hirda IRDA handle. * @retval none */

* @brief Configures the IRDA peripheral. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configurat

* @brief Send an amount of data in non blocking mode. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the

* @brief Initialize some features of ADC common parameters * (all ADC instances belonging to the same ADC common instance) * and

* @brief Disable the selected ADC instance. * @rmtoll CR2 ADON LL_ADC_Disable * @param ADCx ADC instance * @retval None */

* @brief Enable the selected ADC instance. * @note On this STM32 series, after ADC enable, a delay for * ADC internal analog stabiliza

* @brief Set ADC group injected sequencer length and scan direction. * @note This function performs configuration of: * - Sequence leng

* @brief Set ADC group injected conversion trigger source: * internal (SW start) or from external IP (timer event, * external int

* @brief Initialize some features of ADC instance. * @note These parameters have an impact on ADC scope: ADC instance. * Affects both g

* @brief Get ADC calibration state. * @rmtoll CR2 CAL LL_ADC_IsCalibrationOnGoing * @param ADCx ADC instance * @retval 0: cali

* @brief Initialize some features of ADC group regular. * @note These parameters have an impact on ADC scope: ADC group regular. * Refe

* @brief Set ADC group regular conversion data transfer: no transfer or * transfer by DMA, and DMA requests mode. * @note If transfer b

* @brief Set ADC group regular sequencer length and scan direction. * @note Description of ADC group regular sequencer features: * - Fo

* @brief Set ADC group regular conversion trigger source: * internal (SW start) or from external IP (timer event, * external inte

* @brief Start ADC calibration in the mode single-ended * or differential (for devices with differential mode available). * @note On th

* @brief Enable AHB1 peripherals clock. * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n * AHBENR DMA1EN LL_A

* @brief Reset the CRC calculation unit. * @note If Programmable Initial CRC value feature * is available, also set the Data Register t

* @brief Store data in the Independent Data(IDR) register. * @note This register can be used as a temporary storage location for one byte. * @r

* @brief Get DAC enable state of the selected channel. * (0: DAC channel is disabled, 1: DAC channel is enabled) * @rmtoll CR EN1

* @brief Clear Channel 1 global interrupt flag. * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 * @param DMAx DMAx Instance * @retva

* @brief Clear Channel 2 global interrupt flag. * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 * @param DMAx DMAx Instance * @retva

* @brief Clear Channel 3 global interrupt flag. * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 * @param DMAx DMAx Instance * @retva

* @brief Clear Channel 4 global interrupt flag. * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4 * @param DMAx DMAx Instance * @retva

* @brief Clear Channel 5 global interrupt flag. * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5 * @param DMAx DMAx Instance * @retva

* @brief Clear Channel 6 global interrupt flag. * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 * @param DMAx DMAx Instance * @retva

* @brief Clear Channel 7 global interrupt flag. * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 * @param DMAx DMAx Instance * @retva

* @brief Configure all parameters link to DMA transfer. * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n * CCR MEM2M

@defgroup DMA_LL_EF_Configuration Configuration * @{ */ * @brief Enable DMA channel. * @rmtoll CCR EN LL_DMA_EnableChannel

* @brief Set Channel priority level. * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel * @param DMAx DMAx Instance * @param

* @brief Set Data transfer direction (read from peripheral or from memory). * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n

* @brief Set Memory increment mode. * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode * @param DMAx DMAx Instance * @param Channel

* @brief Set Memory size. * @rmtoll CCR MSIZE LL_DMA_SetMemorySize * @param DMAx DMAx Instance * @param Channel This paramet

* @brief Set DMA mode circular or normal. * @note The circular buffer mode cannot be used if the memory-to-memory * data transfer is configured o

* @brief Set Peripheral increment mode. * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode * @param DMAx DMAx Instance * @param Cha

* @brief Set Peripheral size. * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize * @param DMAx DMAx Instance * @param Channel This par

* @brief Clear ExtLine Flags for Lines in range 0 to 31 * @note This bit is set when the selected edge event arrives on the interrupt * li

* @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 * @note The configurable wakeup lines are edge-triggered. No glitch must

* @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 * @note The configurable wakeup lines are edge-triggered. No glitch must b

* @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 * @note This bit is set when the selected edge event arrives on the int

* @brief Locks the FLASH control register access * @retval LL Status */

* @brief Unlock the FLASH control register access * @retval LL Status */

* @brief Enable the remapping of TIM3 alternate function channels 1 to 4 * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_RemapPartial_TIM3

* @brief Return if input data level for several pins of dedicated port is high or low. * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet

* @brief Configure gpio output type for several pins on dedicated port. * @note Output type as to be set when gpio pin is in output or *

* @brief Configure gpio speed for a dedicated pin on dedicated port. * @note I/O speed can be Low, Medium or Fast speed. * @note Warning: onl

* @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. * @note

* @brief Configure the SCL speed. * @note This bit can only be programmed when the I2C is disabled (PE = 0). * @rmtoll CR2 FREQ

* @brief Disable I2C peripheral (PE = 0). * @rmtoll CR1 PE LL_I2C_Disable * @param I2Cx I2C Instance. * @retval None */

* @brief Enable I2C peripheral (PE = 1). * @rmtoll CR1 PE LL_I2C_Enable * @param I2Cx I2C Instance. * @retval None */

* @brief Configure peripheral mode. * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is su

* @brief Set the Own Address1. * @rmtoll OAR1 ADD0 LL_I2C_SetOwnAddress1\n * OAR1 ADD1_7 LL_I2C_SetOwnAdd

* @brief Check if I2S peripheral is enabled * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled * @param SPIx SPI Instance * @retval State o

* @brief This function configures the Cortex-M SysTick source of the time base. * @param HCLKFrequency HCLK frequency in Hz (can be calculated tha

* @brief Set RMVF bit to clear the reset flags. * @rmtoll CSR RMVF LL_RCC_ClearResetFlags * @retval None */

* @brief Get ADCx clock source * @rmtoll CFGR ADCPRE LL_RCC_GetADCClockSource * @param ADCx This parameter can be one of the foll

* @brief Get APB1 prescaler * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler * @retval Returned value can be one of the following val

* @brief Get APB2 prescaler * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler * @retval Returned value can be one of the following val

* @brief Get I2Sx clock source * @rmtoll CFGR2 I2S2SRC LL_RCC_GetI2SClockSource\n * CFGR2 I2S3SRC LL_RCC_GetI2S

* @brief Get USBx clock source * @rmtoll CFGR OTGFSPRE LL_RCC_GetUSBClockSource\n * CFGR USBPRE LL_RCC_GetUSB

* @brief Disable HSE external oscillator (HSE Bypass) * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass * @retval None */

* @brief Enable HSE external oscillator (HSE Bypass) * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass * @retval None */

* @brief Set HSI Calibration trimming * @note user-programmable trimming value that is added to the HSICAL * @note Default value is 16, which, wh

* @brief Enable PLL2 * @rmtoll CR PLL2ON LL_RCC_PLL2_Enable * @retval None */

* @brief Get PLL2 Multiplication Factor * @rmtoll CFGR2 PLL2MUL LL_RCC_PLL2_GetMultiplicator * @retval Returned value can be one of

* @brief Get PLLI2S Multiplication Factor * @rmtoll CFGR2 PLL3MUL LL_RCC_PLLI2S_GetMultiplicator * @retval Returned value can be one

* @brief Check if PLLI2S Ready * @rmtoll CR PLL3RDY LL_RCC_PLLI2S_IsReady * @retval State of bit (1 or 0). */

* @brief Configure PLL2 used for PLL2 Domain * @rmtoll CFGR2 PREDIV2 LL_RCC_PLL_ConfigDomain_PLL2\n * CFGR2 PLL2MUL

* @brief Get PLL multiplication Factor * @rmtoll CFGR PLLMULL LL_RCC_PLL_GetMultiplicator * @retval Returned value can be one of th

* @brief Configure ADC clock source * @rmtoll CFGR ADCPRE LL_RCC_SetADCClockSource * @param ADCxSource This parameter can be one

* @brief Clear Alarm flag * @rmtoll CRL ALRF LL_RTC_ClearFlag_ALR * @param RTCx RTC Instance * @retval None */

* @brief Clear Registers OverFlow flag * @rmtoll CRL OWF LL_RTC_ClearFlag_OW * @param RTCx RTC Instance * @retval None */

* @brief Clear Registers synchronization flag * @rmtoll CRL SECF LL_RTC_ClearFlag_SEC * @param RTCx RTC Instance * @retval

* @brief Set Asynchronous prescaler factor * @rmtoll PRLH PRL LL_RTC_SetAsynchPrescaler\n * @rmtoll PRLL PRL LL_RTC_Set

* @brief Set Output Source * @rmtoll RTCCR CCO LL_RTC_SetOutputSource * @rmtoll RTCCR ASOE LL_RTC_SetOutputSource * @r

* @brief Disable RTC_TAMPx Tamper * @rmtoll CR TPE LL_RTC_TAMPER_Disable\n * @retval None */