Read the FPSCR

Translate code id to code name. some codepage may has another name. If this makes your compilation fail, try replace the string code with one in "icon

Macro: Get the rounding mode bits from the MXCSR control and status register. The rounding mode may contain any of the following flags: _MM_ROUND_NEAR

Loads 128-bit value. : https://msdn.microsoft.com/en-us/library/atzzad1h(v=vs.80).aspx

Shift a right by imm8 bytes while shifting in zeros, and store the results in dst. tmp := imm8[7:0] IF tmp > 15 tmp := 16 FI dst[127:0] := a[127:0] >

For each 8-bit element, if ctrl >= 0 && ctrl < 16 then r = vec[ctrl], else if ctrl < 0 then r = 0

Process a request and update the state of the taskset

------------------------------------------------------------------------------------------------------------------------------ V_MAX3_F32.

------------------------------------------------------------------------------------------------------------------------------ No packed version of ma

/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// //////////////////////////

Applies a type cast to reinterpret four 32-bit floating point values passed in as a 128-bit parameter as packed 32-bit integers. https://msdn.microsof

Compares for inequality. https://msdn.microsoft.com/en-us/library/sf44thbx(v=vs.100).aspx

Converts the four signed 32-bit integer values of a to single-precision, floating-point values https://msdn.microsoft.com/en-us/library/vstudio/36bwxc

Copy the lower 32-bit integer in a to dst. dst[31:0] := a[31:0] https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsi128_si32

Round the packed single-precision (32-bit) floating-point elements in a using the rounding parameter, and store the results as packed single-precision

Interleaves the upper 4 signed or unsigned 16-bit integers in a with the upper 4 signed or unsigned 16-bit integers in b. r0 := a4 r1 := b4 r2 := a5

[AES-WP] Part of Fig. 25 page 32