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hub / github.com/Qucs/qucs / giveNodeNames

Method giveNodeNames

qucs/schematic_file.cpp:1423–1463  ·  view source on GitHub ↗

--------------------------------------------------- Follows the wire lines in order to determine the node names for each component. Output into "stream", NodeSets are collected in "Collect" and counted with "countInit".

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1421// each component. Output into "stream", NodeSets are collected in
1422// "Collect" and counted with "countInit".
1423bool Schematic::giveNodeNames(QTextStream *stream, int& countInit,
1424 QStringList& Collect, QPlainTextEdit *ErrText, int NumPorts)
1425{
1426 // delete the node names
1427 for(Node *pn = DocNodes.first(); pn != 0; pn = DocNodes.next()) {
1428 pn->State = 0;
1429 if(pn->Label) {
1430 if(isAnalog)
1431 pn->Name = pn->Label->Name;
1432 else
1433 pn->Name = "net" + pn->Label->Name;
1434 }
1435 else pn->Name = "";
1436 }
1437
1438 // set the wire names to the connected node
1439 for(Wire *pw = DocWires.first(); pw != 0; pw = DocWires.next())
1440 if(pw->Label != 0) {
1441 if(isAnalog)
1442 pw->Port1->Name = pw->Label->Name;
1443 else // avoid to use reserved VHDL words
1444 pw->Port1->Name = "net" + pw->Label->Name;
1445 }
1446
1447 // go through components
1448 if(!throughAllComps(stream, countInit, Collect, ErrText, NumPorts)){
1449 fprintf(stderr, "Error: Could not go throughAllComps\n");
1450 return false;
1451 }
1452
1453 // work on named nodes first in order to preserve the user given names
1454 throughAllNodes(true, Collect, countInit);
1455
1456 // give names to the remaining (unnamed) nodes
1457 throughAllNodes(false, Collect, countInit);
1458
1459 if(!isAnalog) // collect all node names for VHDL signal declaration
1460 collectDigitalSignals();
1461
1462 return true;
1463}
1464
1465// ---------------------------------------------------
1466bool Schematic::createLibNetlist(QTextStream *stream, QPlainTextEdit *ErrText,

Callers

nothing calls this directly

Calls 1

nextMethod · 0.80

Tested by

no test coverage detected