| 217 | } |
| 218 | |
| 219 | int LoRaClass::parsePacket(int size) |
| 220 | { |
| 221 | int packetLength = 0; |
| 222 | int irqFlags = readRegister(REG_IRQ_FLAGS); |
| 223 | |
| 224 | if (size > 0) { |
| 225 | implicitHeaderMode(); |
| 226 | |
| 227 | writeRegister(REG_PAYLOAD_LENGTH, size & 0xff); |
| 228 | } else { |
| 229 | explicitHeaderMode(); |
| 230 | } |
| 231 | |
| 232 | // clear IRQ's |
| 233 | writeRegister(REG_IRQ_FLAGS, irqFlags); |
| 234 | |
| 235 | if ((irqFlags & IRQ_RX_DONE_MASK) && (irqFlags & IRQ_PAYLOAD_CRC_ERROR_MASK) == 0) { |
| 236 | // received a packet |
| 237 | _packetIndex = 0; |
| 238 | |
| 239 | // read packet length |
| 240 | if (_implicitHeaderMode) { |
| 241 | packetLength = readRegister(REG_PAYLOAD_LENGTH); |
| 242 | } else { |
| 243 | packetLength = readRegister(REG_RX_NB_BYTES); |
| 244 | } |
| 245 | |
| 246 | // set FIFO address to current RX address |
| 247 | writeRegister(REG_FIFO_ADDR_PTR, readRegister(REG_FIFO_RX_CURRENT_ADDR)); |
| 248 | |
| 249 | // put in standby mode |
| 250 | idle(); |
| 251 | } else if (readRegister(REG_OP_MODE) != (MODE_LONG_RANGE_MODE | MODE_RX_SINGLE)) { |
| 252 | // not currently in RX mode |
| 253 | |
| 254 | // reset FIFO address |
| 255 | writeRegister(REG_FIFO_ADDR_PTR, 0); |
| 256 | |
| 257 | // put in single RX mode |
| 258 | writeRegister(REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_RX_SINGLE); |
| 259 | } |
| 260 | |
| 261 | return packetLength; |
| 262 | } |
| 263 | |
| 264 | int LoRaClass::packetRssi() |
| 265 | { |
nothing calls this directly
no outgoing calls
no test coverage detected