| 690 | } |
| 691 | |
| 692 | void LoRaClass::handleDio0Rise() |
| 693 | { |
| 694 | int irqFlags = readRegister(REG_IRQ_FLAGS); |
| 695 | |
| 696 | // clear IRQ's |
| 697 | writeRegister(REG_IRQ_FLAGS, irqFlags); |
| 698 | |
| 699 | if ((irqFlags & IRQ_PAYLOAD_CRC_ERROR_MASK) == 0) { |
| 700 | |
| 701 | if ((irqFlags & IRQ_RX_DONE_MASK) != 0) { |
| 702 | // received a packet |
| 703 | _packetIndex = 0; |
| 704 | |
| 705 | // read packet length |
| 706 | int packetLength = _implicitHeaderMode ? readRegister(REG_PAYLOAD_LENGTH) : readRegister(REG_RX_NB_BYTES); |
| 707 | |
| 708 | // set FIFO address to current RX address |
| 709 | writeRegister(REG_FIFO_ADDR_PTR, readRegister(REG_FIFO_RX_CURRENT_ADDR)); |
| 710 | |
| 711 | if (_onReceive) { |
| 712 | _onReceive(packetLength); |
| 713 | } |
| 714 | } |
| 715 | else if ((irqFlags & IRQ_TX_DONE_MASK) != 0) { |
| 716 | if (_onTxDone) { |
| 717 | _onTxDone(); |
| 718 | } |
| 719 | } |
| 720 | } |
| 721 | } |
| 722 | |
| 723 | uint8_t LoRaClass::readRegister(uint8_t address) |
| 724 | { |