| 946 | #if defined(__AVR__) |
| 947 | #if defined(INT0_vect) && CORE_NUM_INTERRUPT > 0 |
| 948 | ISR(INT0_vect) { Encoder::update(Encoder::interruptArgs[SCRAMBLE_INT_ORDER(0)]); } |
| 949 | #endif |
| 950 | #if defined(INT1_vect) && CORE_NUM_INTERRUPT > 1 |
| 951 | ISR(INT1_vect) { Encoder::update(Encoder::interruptArgs[SCRAMBLE_INT_ORDER(1)]); } |