| 783 | } |
| 784 | |
| 785 | inline void queryCacheSizes_intel_direct(int& l1, int& l2, int& l3) |
| 786 | { |
| 787 | int abcd[4]; |
| 788 | l1 = l2 = l3 = 0; |
| 789 | int cache_id = 0; |
| 790 | int cache_type = 0; |
| 791 | do { |
| 792 | abcd[0] = abcd[1] = abcd[2] = abcd[3] = 0; |
| 793 | EIGEN_CPUID(abcd,0x4,cache_id); |
| 794 | cache_type = (abcd[0] & 0x0F) >> 0; |
| 795 | if(cache_type==1||cache_type==3) // data or unified cache |
| 796 | { |
| 797 | int cache_level = (abcd[0] & 0xE0) >> 5; // A[7:5] |
| 798 | int ways = (abcd[1] & 0xFFC00000) >> 22; // B[31:22] |
| 799 | int partitions = (abcd[1] & 0x003FF000) >> 12; // B[21:12] |
| 800 | int line_size = (abcd[1] & 0x00000FFF) >> 0; // B[11:0] |
| 801 | int sets = (abcd[2]); // C[31:0] |
| 802 | |
| 803 | int cache_size = (ways+1) * (partitions+1) * (line_size+1) * (sets+1); |
| 804 | |
| 805 | switch(cache_level) |
| 806 | { |
| 807 | case 1: l1 = cache_size; break; |
| 808 | case 2: l2 = cache_size; break; |
| 809 | case 3: l3 = cache_size; break; |
| 810 | default: break; |
| 811 | } |
| 812 | } |
| 813 | cache_id++; |
| 814 | } while(cache_type>0 && cache_id<16); |
| 815 | } |
| 816 | |
| 817 | inline void queryCacheSizes_intel_codes(int& l1, int& l2, int& l3) |
| 818 | { |
no outgoing calls
no test coverage detected