| 199 | } |
| 200 | |
| 201 | void V_Core::PlainDMAWrite(u16* pMem, u32 size) |
| 202 | { |
| 203 | if (SPU2::MsgToConsole()) |
| 204 | { |
| 205 | // Don't need this anymore. Target may still be good to know though. |
| 206 | /*if((uptr)pMem & 15) |
| 207 | { |
| 208 | ConLog("* SPU2 DMA Write > Misaligned source. Core: %d IOP: %p TSA: 0x%x Size: 0x%x\n", Index, (void*)pMem, TSA, size); |
| 209 | }*/ |
| 210 | |
| 211 | if (ActiveTSA & 7) |
| 212 | { |
| 213 | SPU2::ConLog("* SPU2 DMA Write > Misaligned target. Core: %d IOP: %p TSA: 0x%x Size: 0x%x\n", Index, (void*)DMAPtr, ActiveTSA, ReadSize); |
| 214 | } |
| 215 | } |
| 216 | |
| 217 | TimeUpdate(psxRegs.cycle); |
| 218 | |
| 219 | ReadSize = size; |
| 220 | IsDMARead = false; |
| 221 | DMAICounter = 0; |
| 222 | LastClock = psxRegs.cycle; |
| 223 | Regs.STATX &= ~0x80; |
| 224 | Regs.STATX |= 0x400; |
| 225 | TADR = MADR + (size << 1); |
| 226 | |
| 227 | if (SPU2::MsgDMA()) |
| 228 | { |
| 229 | SPU2::ConLog("* SPU2: DMA%c Write Transfer of %d bytes to %x (%02x %x %04x). IRQE = %d IRQA = %x \n", |
| 230 | GetDmaIndexChar(), size << 1, ActiveTSA, DMABits, AutoDMACtrl, Regs.ATTR & 0xffff, |
| 231 | Cores[Index].IRQEnable, Cores[Index].IRQA); |
| 232 | } |
| 233 | |
| 234 | FinishDMAwrite(); |
| 235 | } |
| 236 | |
| 237 | void V_Core::FinishDMAwrite() |
| 238 | { |
nothing calls this directly
no test coverage detected