| 440 | } |
| 441 | |
| 442 | void V_Core::DoDMAread(u16* pMem, u32 size) |
| 443 | { |
| 444 | TimeUpdate(psxRegs.cycle); |
| 445 | |
| 446 | DMARPtr = pMem; |
| 447 | ActiveTSA = TSA & 0xfffff; |
| 448 | ReadSize = size; |
| 449 | IsDMARead = true; |
| 450 | LastClock = psxRegs.cycle; |
| 451 | DMAICounter = (std::min(ReadSize, (u32)0x100) * CYCLES_PER_WORD); |
| 452 | Regs.STATX &= ~0x80; |
| 453 | Regs.STATX |= 0x400; |
| 454 | //Regs.ATTR |= 0x30; |
| 455 | TADR = MADR + (size << 1); |
| 456 | |
| 457 | CounterUpdate(DMAICounter); |
| 458 | |
| 459 | if (SPU2::MsgDMA()) |
| 460 | { |
| 461 | SPU2::ConLog("* SPU2: DMA%c Read Transfer of %d bytes from %x (%02x %x %04x). IRQE = %d IRQA = %x \n", |
| 462 | GetDmaIndexChar(), size << 1, ActiveTSA, DMABits, AutoDMACtrl, Regs.ATTR & 0xffff, |
| 463 | Cores[Index].IRQEnable, Cores[Index].IRQA); |
| 464 | } |
| 465 | } |
| 466 | |
| 467 | void V_Core::DoDMAwrite(u16* pMem, u32 size) |
| 468 | { |
no test coverage detected