| 434 | } |
| 435 | |
| 436 | bool CMipsInstruction::LoadEncoding(const tMipsOpcode& SourceOpcode, const char* Line) |
| 437 | { |
| 438 | immediateType = MIPS_NOIMMEDIATE; |
| 439 | registers.reset(); |
| 440 | |
| 441 | if (vfpuSize == -1) |
| 442 | { |
| 443 | if (SourceOpcode.flags & MO_VFPU_SINGLE) |
| 444 | vfpuSize = 0; |
| 445 | else if (SourceOpcode.flags & MO_VFPU_QUAD) |
| 446 | vfpuSize = 3; |
| 447 | } |
| 448 | |
| 449 | const char* SourceEncoding = SourceOpcode.encoding; |
| 450 | |
| 451 | while (*Line == ' ' || *Line == '\t') Line++; |
| 452 | |
| 453 | if (!(*SourceEncoding == 0 && *Line == 0)) |
| 454 | { |
| 455 | int RetLen; |
| 456 | while (*SourceEncoding != 0) |
| 457 | { |
| 458 | while (*Line == ' ' || *Line == '\t') Line++; |
| 459 | if (*Line == 0) return false; |
| 460 | |
| 461 | switch (*SourceEncoding) |
| 462 | { |
| 463 | case 'T': // float reg |
| 464 | if (!MipsGetRegister(Line,RetLen,registers.frt, MipsFloatRegisters)) return false; |
| 465 | Line += RetLen; |
| 466 | SourceEncoding++; |
| 467 | break; |
| 468 | case 'D': // float reg |
| 469 | if (!MipsGetRegister(Line,RetLen,registers.frd, MipsFloatRegisters)) return false; |
| 470 | Line += RetLen; |
| 471 | SourceEncoding++; |
| 472 | break; |
| 473 | case 'S': // float reg |
| 474 | if (!MipsGetRegister(Line,RetLen,registers.frs, MipsFloatRegisters)) return false; |
| 475 | Line += RetLen; |
| 476 | SourceEncoding++; |
| 477 | break; |
| 478 | case 't': |
| 479 | if (!MipsGetRegister(Line,RetLen,registers.grt, MipsRegisters)) return false; |
| 480 | Line += RetLen; |
| 481 | SourceEncoding++; |
| 482 | break; |
| 483 | case 'd': |
| 484 | if (!MipsGetRegister(Line,RetLen,registers.grd, MipsRegisters)) return false; |
| 485 | Line += RetLen; |
| 486 | SourceEncoding++; |
| 487 | break; |
| 488 | case 's': |
| 489 | if (!MipsGetRegister(Line,RetLen,registers.grs, MipsRegisters)) return false; |
| 490 | Line += RetLen; |
| 491 | SourceEncoding++; |
| 492 | break; |
| 493 | case 'V': // ps2 vector registers |
nothing calls this directly
no test coverage detected