| 438 | #define NUM_LANES 16 |
| 439 | |
| 440 | void DisassemblyFunction::generateBranchLines() |
| 441 | { |
| 442 | struct LaneInfo |
| 443 | { |
| 444 | bool used; |
| 445 | u32 end; |
| 446 | }; |
| 447 | |
| 448 | LaneInfo lanes[NUM_LANES]; |
| 449 | for (int i = 0; i < NUM_LANES; i++) { |
| 450 | lanes[i].used = false; |
| 451 | lanes[i].end = 0; |
| 452 | } |
| 453 | |
| 454 | u32 end = address+size; |
| 455 | |
| 456 | for (u32 funcPos = address; funcPos < end; funcPos += 4) |
| 457 | { |
| 458 | MIPSAnalyst::MipsOpcodeInfo opInfo = MIPSAnalyst::GetOpcodeInfo(cpu,funcPos); |
| 459 | |
| 460 | bool inFunction = (opInfo.branchTarget >= address && opInfo.branchTarget < end); |
| 461 | if (opInfo.isBranch && !opInfo.isBranchToRegister && !opInfo.isLinkedBranch && inFunction) |
| 462 | { |
| 463 | BranchLine line; |
| 464 | line.laneIndex = 0; |
| 465 | if (opInfo.branchTarget < funcPos) |
| 466 | { |
| 467 | line.first = opInfo.branchTarget; |
| 468 | line.second = funcPos; |
| 469 | line.type = LINE_UP; |
| 470 | } else { |
| 471 | line.first = funcPos; |
| 472 | line.second = opInfo.branchTarget; |
| 473 | line.type = LINE_DOWN; |
| 474 | } |
| 475 | |
| 476 | lines.push_back(line); |
| 477 | } |
| 478 | } |
| 479 | |
| 480 | std::sort(lines.begin(),lines.end()); |
| 481 | for (size_t i = 0; i < lines.size(); i++) |
| 482 | { |
| 483 | for (int l = 0; l < NUM_LANES; l++) |
| 484 | { |
| 485 | if (lines[i].first > lanes[l].end) |
| 486 | lanes[l].used = false; |
| 487 | } |
| 488 | |
| 489 | int lane = -1; |
| 490 | for (int l = 0; l < NUM_LANES; l++) |
| 491 | { |
| 492 | if (!lanes[l].used) |
| 493 | { |
| 494 | lane = l; |
| 495 | break; |
| 496 | } |
| 497 | } |
nothing calls this directly
no test coverage detected