| 649 | } |
| 650 | |
| 651 | void _deleteGPRtoXMMreg(int reg, int flush) |
| 652 | { |
| 653 | for (uint i = 0; i < iREGCNT_XMM; i++) |
| 654 | { |
| 655 | |
| 656 | if (xmmregs[i].inuse && xmmregs[i].type == XMMTYPE_GPRREG && xmmregs[i].reg == reg) |
| 657 | { |
| 658 | |
| 659 | switch (flush) |
| 660 | { |
| 661 | case DELETE_REG_FREE: |
| 662 | _freeXMMreg(i); |
| 663 | break; |
| 664 | case DELETE_REG_FLUSH: |
| 665 | case DELETE_REG_FLUSH_AND_FREE: |
| 666 | if (xmmregs[i].mode & MODE_WRITE) |
| 667 | { |
| 668 | pxAssert(reg != 0); |
| 669 | |
| 670 | //pxAssert( g_xmmtypes[i] == XMMT_INT ); |
| 671 | xMOVDQA(ptr[&cpuRegs.GPR.r[reg].UL[0]], xRegisterSSE(i)); |
| 672 | |
| 673 | // get rid of MODE_WRITE since don't want to flush again |
| 674 | xmmregs[i].mode &= ~MODE_WRITE; |
| 675 | xmmregs[i].mode |= MODE_READ; |
| 676 | } |
| 677 | |
| 678 | if (flush == DELETE_REG_FLUSH_AND_FREE) |
| 679 | xmmregs[i].inuse = 0; |
| 680 | break; |
| 681 | |
| 682 | case DELETE_REG_FREE_NO_WRITEBACK: |
| 683 | xmmregs[i].inuse = 0; |
| 684 | break; |
| 685 | } |
| 686 | |
| 687 | return; |
| 688 | } |
| 689 | } |
| 690 | } |
| 691 | |
| 692 | // Flush is 0: _freeXMMreg. Flush in memory if MODE_WRITE. Clear inuse |
| 693 | // Flush is 1: Flush in memory. But register is still valid |
no test coverage detected