| 352 | // PGIF registers I/O handlers: |
| 353 | |
| 354 | void PGIFw(int addr, u32 data) |
| 355 | { |
| 356 | //if (((addr != PGIF_CTRL) || (addr != PGPU_STAT) || ((addr == PGIF_CTRL) && (getUpdPgifCtrlReg() != data))) && (addr != PGPU_STAT)) |
| 357 | REG_LOG("PGIF write 0x%08X = 0x%08X 0x%08X EEpc= %08X IOPpc= %08X ", addr, data, getUpdPgifCtrlReg(), cpuRegs.pc, psxRegs.pc); |
| 358 | |
| 359 | switch (addr) |
| 360 | { |
| 361 | case PGPU_STAT: |
| 362 | pgpu.stat.write(data); //Should all bits be writable? |
| 363 | break; |
| 364 | case PGIF_CTRL: |
| 365 | pgif.ctrl.write(data); |
| 366 | fillFifoOnDrain(); //Now this checks the 0x8 bit of the PGIF_CTRL reg, so it here too, |
| 367 | break; //so that it gets updated immediately once it is set. |
| 368 | case IMM_E2: |
| 369 | pgif.imm_response.reg.e2 = data; |
| 370 | break; |
| 371 | case IMM_E3: |
| 372 | pgif.imm_response.reg.e3 = data; |
| 373 | break; |
| 374 | case IMM_E4: |
| 375 | pgif.imm_response.reg.e4 = data; |
| 376 | break; |
| 377 | case IMM_E5: |
| 378 | pgif.imm_response.reg.e5 = data; |
| 379 | break; |
| 380 | case PGPU_CMD_FIFO: |
| 381 | Console.Error("PGIF CMD FIFO write by EE (SHOULDN'T HAPPEN) 0x%08X = 0x%08X", addr, data); |
| 382 | break; |
| 383 | case PGPU_DAT_FIFO: |
| 384 | ringBufPut(&rb_gp0, &data); |
| 385 | // Console.WriteLn( "\n\r PGIF REVERSE !!! DATA write 0x%08X = 0x%08X IF_CTRL= %08X PGPU_STAT= %08X CmdCnt 0x%X \n\r", addr, data, getUpdPgifCtrlReg(), getUpdPgpuStatReg(), rb_gp1.count); |
| 386 | drainPgpuDmaNrToIop(); |
| 387 | break; |
| 388 | default: |
| 389 | DevCon.Error("PGIF write to unknown location 0xx% , data: %x", addr, data); |
| 390 | break; |
| 391 | } |
| 392 | } |
| 393 | |
| 394 | // Read PGIF Hardware Registers. |
| 395 | u32 PGIFr(int addr) |
no test coverage detected